Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Processor Uncore Configuration Registers
142
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
13.2.4.23 TCMR2SHADOW
Timing Constraints MR2 Shadow Timing Parameter 
11:0
RW
0x100
T_XSDLL (t_xsdll):
Exit Self Refresh to commands requiring a locked DLL in the range of 128 to 
4095 DCLK cycles
Type:
CFG
PortID: N/A
Bus:
1
Device: 16
Function:
0,1,4,5
Bus:
1
Device: 30
Function:
0,1,4,5
Offset:
0x218
Bit
Attr
Default
Description
Type:
CFG
PortID: N/A
Bus:
1
Device: 16
Function:
0,1,4,5
Bus:
1
Device: 30
Function:
0,1,4,5
Offset:
0x21c
Bit
Attr
Default
Description
31:27
RV
-
Reserved.
26:24
RW_LV
0x0
ADDR_BIT_SWIZZLE (addr_bit_swizzle):
Each bit is set in case of the corresponding 2-rank UDIMM or certain 
LRDIMM requires address mirroring/swizzling. It indicates that some of the 
address bits are swizzled for rank 1 (or rank 3), and this has to be 
considered in MRS command. The address swizzling bits:
A3 and A4
A5 and A6
A7 and A8
BA0 and BA1
Bit 24 refers to DIMM 0
Bit 25 refers to DIMM 1
Bit 26 refers to DIMM 2 
23:16
RW
0x2
MR2_SHDW_A15TO8 (mr2_shdw_a15to8):
Copy of MR2 A[15:8] shadow.
Bit 23-19: zero, copy of MR2 A[15:11], reserved for future JEDEC use
Bit 18-17: Rtt_WR, that is, copy of MR2 A[10:9]
Bit 16: zero, copy of MR2 A[8], reserved for future JEDEC use
15:15
RV
-
Reserved.
14:12
RW
0x0
MR2_SHDW_A7_SRT (mr2_shdw_a7_srt):
Copy of MR2 A[7] shadow which defines per DIMM availability of SRT mode - 
set if extended temperature range and ASR is not supported, otherwise 
cleared
Bit 14: DIMM 2
Bit 13: DIMM 1
Bit 12: 
DIMM 0
11:11
RV
-
Reserved.
10:8
RW
0x0
MR2_SHDW_A6_ASR (mr2_shdw_a6_asr):
Copy of MR2 A[6] shadow which defines per DIMM availability of ASR mode 
- set if Auto Self-Refresh (ASR) is supported, otherwise cleared
Bit 10: DIMM 2
Bit 9: DIMM 1
Bit 8: DIMM 0
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