Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Integrated I/O (IIO) Configuration Registers
198
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
14.2.4
PCISTS
Type:
CFG
PortID:
N/A
Bus:
0
Device:
0Function:0
Bus:
0
Device:
2Function:0-3
Bus:
0
Device:
3Function:0-3
Offset:
0x6
Bit
Attr
Default
Description
15:15
RW1C
0x0
dpe:
Detected Parity Error  
This bit is set by a root port when it receives a packet on the primary side 
with an uncorrectable data error (including a packet with poison bit set) or 
an uncorrectable address/control parity error. The setting of this bit is 
regardless of the Parity Error Response bit (PERRE) in the PCICMD register.
14:14
RW1C
0x0
sse:
Signaled System Error  
1: The root port reported fatal/nonfatal (and not correctable) errors it 
detected on its PCI Express interface to the IIO core error logic (which might 
eventually escalate the error through the ERR[2:0] pins or message to cpu 
core or message to PCH). Note that the SERRE bit in the PCICMD register 
must be set for a device to report the error the IIO core error logic.Software 
clears this bit by writing a ‘1’ to it. This bit is also set (when SERR enable bit 
is set) when a FATAL/NONFATAL message is forwarded to the IIO core error 
logic. Note that the IIO internal ‘core’ errors (like parity error in the internal 
queues) are not reported via this bit.
0: The root port did not report a fatal/nonfatal error
13:13
RW1C
0x0
rma:
Received Master Abort  
This bit is set when a root port experiences a master abort condition on a 
transaction it mastered on the primary interface (uncore internal bus).
Note that certain errors might be detected right at the PCI Express interface 
and those transactions might not ’propagate’ to the primary interface before 
the error is detected (for example, accesses to memory above TOCM in 
cases where the PCIe* interface logic itself might have visibility into TOCM). 
Such errors do not cause this bit to be set, and are reported via the PCI 
Express interface error bits (secondary status register).
Conditions that cause bit 13 to be set, include:
Device receives a completion on the primary interface (internal bus of 
uncore) with Unsupported Request or master abort completion Status. This 
includes UR status received on the primary side of a PCI Express port on 
peer-to-peer completions also. 
Hardware will not set this bit while in DMI mode.
12:12
RW1C
0x0
rta:
Received Target Abort
This bit is set when a device experiences a completer abort condition on a 
transaction it mastered on the primary interface (uncore internal bus). Note 
that certain errors might be detected right at the PCI Express interface and 
those transactions might not ’propagate’ to the primary interface before the 
error is detected (for example, accesses to memory above VTBAR). Such 
errors do not cause this bit to be set, and are reported via the PCI Express 
interface error bits (secondary status register).
Conditions that cause bit 12 to be set, include:
Device receives a completion on the primary interface (internal bus of 
uncore) with completer abort completion Status. This includes CA status 
received on the primary side of a PCI Express port on peer-to-peer 
completions also. 
Hardware will not set this bit while in DMI mode.
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