Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Integrated I/O (IIO) Configuration Registers
224
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
14.2.46 LNKCON
PCI Express Link Control
The PCI Express Link Control register controls the PCI Express Link specific parameters. 
The link control register needs some default values setup by the local host.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
0Function:0 (DMI2 Mode)
Offset:
0x1b0
Bus:
0
Device:
0Function:0 (PCIe* Mode)
Bus:
0
Device:
2Function:0-3
Bus:
0
Device:
3Function:0-3
Offset:
0xa0
Bit
Attr
Default
Description
15:12
RV
-
Reserved. 
11:11
RW
0x0
link_autonomous_bandwidth_interrupt_enable:
For root ports, when set to 1b this bit enables the generation of an 
interrupt to indicate that the Link Autonomous Bandwidth Status 
bit has been set.For DMI mode on Dev#0, interrupt is not 
supported and hence this bit is not useful. Expectation is that BIOS 
will set bit 27 in MISCCTRLSTS to notify the system of autonomous 
BW change event on that port.
10:10
RW
0x0
link_bandwidth_management_interrupt_enable:
For root ports, when set to 1b this bit enables the generation of an 
interrupt to indicate that the Link Bandwidth Management Status 
bit has been set.For DMI mode on Dev#0, interrupt is not 
supported and hence this bit is not useful. Expectation is that BIOS 
will set bit 27 in MISCCTRLSTS to notify the system of autonomous 
BW change event on that port.
9:9
RW
0x0
hardware_autonomous_width_disable:
When Set, this bit disables hardware from changing the Link width 
for reasons other than attempting to correct unreliable Link 
operation by reducing Link width. Note that IIO does not by itself 
change width for any reason other than reliability. So this bit only 
disables such a width change as initiated by the device on the other 
end of the link.
8:8
RO
0x0
enable_clock_power_management:
N/A for processor.
7:7
RW
0x0
extended_synch:
This bit when set forces the transmission of additional ordered sets 
when exiting L0s and when in recovery. See PCI Express Base 
Specification, Revision 2.0 for details.
6:6
RW_V (Function 0)
RW (Function 1-3)
0x0
common_clock_configuration:
Software sets this bit to indicate that this component and the 
component at the opposite end of the Link are operating with a 
common clock source. A value of 0b indicates.
that this component and the component at the opposite end of the 
Link are operating with separate reference clock sources. Default 
value of this bit is 0b.
Components utilize this common clock configuration information to 
report the correct L0s and L1 Exit Latencies in the NFTS.
The values used come from these registers depending on the value 
of this bit:
0: Use NFTS values from CLSPHYCTL3
1: Use NFTS values from CLSPHYCTL4 
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