Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Integrated I/O (IIO) Configuration Registers
226
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
14.2.47 LNKSTS
PCI Express Link Status 
The PCI Express Link Status register provides information on the status of the PCI 
Express Link such as negotiated width, training, and so forth. The link status register 
needs some default values setup by the local host. 
Type:
CFG
PortID:
N/A
Bus:
0
Device:
0Function:0 (DMI2 Mode)
Offset:
0x1b2
Bus:
0
Device:
0Function:0 (PCIe* Mode)
Bus:
0
Device:
2Function:0-3
Bus:
0
Device:
3Function:0-3
Offset:
0xa2
Bit
Attr
Default
Description
15:15
RW1C
0x0
link_autonomous_bandwidth_status:
This bit is set to 1b by hardware to indicate that hardware has autonomously 
changed link speed or width, without the port transitioning through 
DL_Down status, for reasons other than to attempt to correct unreliable link 
operation. IIO does not, on its own, change speed or width autonomously 
for unreliability reasons. IIO only sets this bit when it receives a width or 
speed change indication from downstream component that is not for link 
reliability reasons.
14:14
RW1C
0x0
link_bandwidth_management_status:
This bit is set to 1b by hardware to indicate that either of the following has 
occurred without the port transitioning through DL_Down status:
a) A link retraining initiated by a write of 1b to the Retrain Link bit has 
completed
b) Hardware has autonomously changed link speed or width to attempt to 
correct unreliable link operation
Note IIO also sets this bit when it receives a width or speed change 
indication from downstream component that is for link reliability reasons.
13:13
RO_V
0x0
data_link_layer_link_active:
Set to 1b when the Data Link Control and Management State Machine is in 
the DL_Active state, 0b otherwise.When this bit is 0b, the transaction layer 
associated with the link will abort all transactions that would otherwise be 
routed to that link.
12:12
RW_O
0x1
slot_clock_configuration:
This bit indicates whether the processor receives clock from the same xtal 
that also provides clock to the device on the other end of the link.
1: indicates that same xtal provides clocks to the processor and the slot or 
device on other end of the link
0: indicates that different xtals provide clocks to the processor and the slot 
or device on other end of the link
In general, this field is expected to be set to 1b by BIOS based on board 
clock routing. This bit has to be set to 1b on DMI mode operation on 
Device#0.
downloadlike
ArtboardArtboardArtboard
Report Bug