Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Integrated I/O (IIO) Configuration Registers
232
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
14.2.50 SLTSTS
PCI Express Slot Status 
The PCI Express Slot Status register defines important status information for 
operations such as hot-plug and Power Management.
0:0
RW
0x0
attention_button_pressed_enable:
This bit enables the generation of hot-plug interrupts or wake messages via 
an attention button pressed event.
0: disables generation of hot-plug interrupts or wake messages when the 
attention button is pressed.
1: Enables generation of hot-plug interrupts or wake messages when the 
attention button is pressed.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
0Function:0 (PCIe* Mode)
Bus:
0
Device:
2Function:0-3
Bus:
0
Device:
3Function:0-3
Offset:
0xa8
Bit
Attr
Default
Description
Type:
CFG
PortID:
N/A
Bus:
0
Device:
0Function:0 (PCIe* Mode)
Bus:
0
Device:
2Function:0-3
Bus:
0
Device:
3Function:0-3
Offset:
0xaa
Bit
Attr
Default
Description
15:9
RV
-
Reserved. 
8:8
RW1C
0x0
data_link_layer_state_changed:
This bit is set (if it is not already set) when the state of the Data Link Layer 
Link Active bit in the Link Status register changes. Software must read Data 
Link Layer Active field to determine the link state before initiating 
configuration cycles to the hot plugged device.
7:7
RO_V
0x0
electromechanical_latch_status:
When read this register returns the current state of the Electromechanical 
Interlock (the EMILS pin) which has the defined encodings as:
0: Electromechanical Interlock Disengaged
1: Electromechanical Interlock Engaged
6:6
RO_V
0x0
presence_detect_state:
For ports with slots (where the Slot Implemented bit of the PCI Express 
Capabilities Registers is 1b), this field is the logical OR of the Presence Detect 
status determined via an in-band mechanism and sideband Present Detect 
pins. Refer to how PCI Express Base Specification, Revision 2.0 for how the 
inband presence detect mechanism works (certain states in the LTSSM 
constitute “card present” and others don’t).
0: Card/Module slot empty
1: Card/module Present in slot (powered or unpowered)
For ports with no slots, IIO hardwires this bit to 1b.
Note: OS could get confused when it sees an empty PCI Express root port 
that is, 'no slots + no presence', since this is now disallowed in the spec. So 
bios must hide all unused root ports devices in IIO config space, via the 
DEVHIDE register.
Refer to RAS Chapter for details of how this bit is shifted in on the VPP bit 
stream.
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