Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
319
Datasheet Volume Two: Functional Description, February 2014
Integrated I/O (IIO) Configuration Registers
14.4.18 MSIXMSGCTL
MSI-X Message Control.
14.4.19 TABLEOFF_BIR
MSI-X Table Offset and BAR Indicator.
14.4.20 PBAOFF_BIR
Type:
CFG
PortID:
N/A
Bus:
0
Device:
4Function:0-7
Offset:
0x82
Bit
Attr
Default
Description
15:15
RW
0x0
msi_x_enable:
Software uses this bit to select between MSI-X or INTx method for signaling 
interrupts from the DMA
0: INTx method is chosen for DMA interrupts
1: MSI-X method is chosen for DMA interrupts
14:14
RW
0x0
function_mask:
If 1, the 1 vector associated with the dma is masked, regardless of the per-
vector mask bit state. 
If 0, the vector’s mask bit determines whether the vector is masked or not. 
Setting or clearing the MSI-X function mask bit has no effect on the state of 
the per-vector Mask bit.
13:11
RV
-
Reserved. 
10:0
RO
0x0
table_size:
Indicates the MSI-X table size which for IIO is 1, encoded as a value of 0h.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
4Function:0-7
Offset:
0x84
Bit
Attr
Default
Description
31:3
RO
0x400
table_offset:
MSI-X Table Structure is at offset 8K from the Intel® Quick Data DMA BAR 
address. See “MSI-X Lower Address Registers (MSGADDR)” for the start of 
details relating to MSI-X registers.
2:0
RO
0x0
table_bir:
Intel® Quick Data DMA BAR is at offset 10h in the DMA config space and 
hence this register is 0.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
4Function:0-7
Offset:
0x88
Bit
Attr
Default
Description
31:3
RO
0x600
table_offset:
MSI-X PBA Structure is at offset 12K from the Intel® Quick Data DMA BAR 
address. See xref for details.
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