Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Integrated I/O (IIO) Configuration Registers
342
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
Setting more than one of these bits with the same write operation will result in an Fatal 
error affiliated.
14.5.15 DMACOUNT
DMA Descriptor Count Register.
14.5.16 CHANSTS_0
Channel Status 0 Register.
The Channel Status Register records the address of the last descriptor completed by 
the DMA channel. Refer to Intel® Quick Data Architecture Specification 2.0 Rev 1.0 for 
special hardware requirements when software reads this register.
Type:
MEM
PortID:
8’h7e
Bus:
0
Device:
4Function:0-7
Offset:
0x84
Bit
Attr
Default
Description
7:6
RV
-
Reserved. 
5:5
RW_LV
0x0
reset_dma:
Set this bit to reset the DMA channel. Setting this bit is a last resort to 
recover the DMA channel from a programming error or other problem such 
as dead lock from cache coherency protocol. Execution of this command does 
not generate an interrupt or generate status. This command causes the DMA 
channel to return to a known state Halted.This field is RW if CHANCNT 
register is 1 otherwise this register is RO.
4:3
RV
-
Reserved. 
2:2
RW_LV
0x0
susp_dma:
Suspend DMA. Set this bit to suspend the current DMA transfer. This field is 
RW if CHANCNT register is 1 otherwise this register is RO.
1:0
RV
-
Reserved. 
Type:
MEM
PortID:
8’h7e
Bus:
0
Device:
4Function:0-7
Offset:
0x86
Bit
Attr
Default
Description
15:0
RW_L
0x0
numdesc:
This is the absolute value of the number of valid descriptors in the chain. The 
hardware sets this register and an internal counter to zero whenever the 
CHAINADDR register is written. When this register does not equal the value 
of the internal register, the DMA channel processes descriptors, incrementing 
the internal counter each time that it completes (or skips) a descriptor.This 
register is RW if CHANCNT register is 1 otherwise this register is RO.
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