Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
343
Datasheet Volume Two: Functional Description, February 2014
Integrated I/O (IIO) Configuration Registers
Type:
MEM
PortID:
8’h7e
Bus:
0
Device:
4Function:0-7
Offset:
0x88
Bit
Attr
Default
Description
31:6
RO
0x0
cmpdscaddr:
This register stores the upper address bits (64B aligned) of the last descriptor 
processed. The DMA channel automatically updates this register when an 
error or successful completion occurs. For each completion, the DMA channel 
over-writes the previous value regardless of whether that value has been 
read.
5:3
RV
-
Reserved. 
2:0
RO
0x3
dma_trans_state:
DMA Transfer Status. The DMA engine sets these bits indicating the state of 
the current DMA transfer. The cause of an abort can be either error during the 
DMA transfer or invoked by the controlling process via the CHANCMD 
register.000 - Active
001 - Idle, DMA Transfer Done (no hard errors)
010 - Suspended
011 - Halted, operation aborted (refer to Channel Error register for further 
detail)
100 - Armed
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