Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
367
Datasheet Volume Two: Functional Description, February 2014
Integrated I/O (IIO) Configuration Registers
14.6.29 MENCMEM_BASE
Intel
®
 Management Engine (Intel
®
ME) noncoherent memory base address.
14.6.30 MENCMEM_LIMIT
Intel
® 
Management Engine (Intel
®
 ME) noncoherent Memory Base Limit.
14.6.31 CPUBUSNO
CPU Internal Bus Numbers.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
5Function:0
Offset:
0xf0
Bit
Attr
Default
Description
63:19
RW_LB
0x1fffffffffff
addr:
Intel
®
 Management Engine (Intel
®
ME) UMA Base Address. Indicates the 
base address which is aligned to a 1MB boundary. Bits [63:19] 
corresponds to A[63:19] address bits. 
18:0
RV
-
Reserved.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
5Function:0
Offset:
0xf8
Bit
Attr
Default
Description
63:19
RW_LB
0x0
addr:
Intel
®
ME UMA Limit Address. Indicates the limit address which is aligned to 
a 1MB boundary. Bits [63:19] corresponds to A[63:19] address bits.Any 
address that falls within MENCMEMBASE <= Addr <= MENCMEMLIMIT 
range is considered to target the UMA range. Setting the MCNCMEMBASE 
greater than the MCNCMEMLIMIT disables this range. 
The range indicated by this register must fall within the low dram or high 
dram memory regions as described via the corresponding base and limit 
registers. 
18:0
RV
-
Reserved.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
5Function:0
Offset:
0x108
Bit
Attr
Default
Description
31:25
RV
-
Reserved.
24:17
RW_LB
0x0
segment:
16:16
RW_LB
0x0
valid:
1: IIO claims PCI config accesses from ring if:
the bus# matches the value in bits 7:0 of this register and Dev# >= 16
OR
the bus# does not match either the value in bits 7:0 or 15:8 of this register
0: IIO does not claim PCI config accesses from ring
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