Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
371
Datasheet Volume Two: Functional Description, February 2014
Integrated I/O (IIO) Configuration Registers
11:9
RW
0x0
rrbsize:
Specifies the number of entries used in each half of the write cache. The 
default is to use all entries.
0000: 104 each side (208 total)
0001: 96 each side (192 total)
0010: 88 each side (176 total)
0011: 80 each side (160 total)
0100: 72 each side (144 total)
0101: 64 each side (128 total)
0110: 56 each side (112 tota)l
0111: 48 each side (96 total)
1000: 40 each side (80 total)
1001: 32 each side (64 total)
1010: 24 each side (48 total)
1011: 16 each side (32 total)
1100: 8 each side (16 total)
Others = Invalid
Used to limit performance for tuning purposes. rrbsize3 is located at 
CIPCTRL bit 16.
This mode should not be used in conjunction with ctagentry_avail_mask in 
IRP_MISC_DFX2 / IRP_MISC_DFX3.
8:6
RW
0x1
numrtid_vcp:
000: 0
001: 1
010: 2
011: 3
100: 4
Others: Reserved
5:3
RW
0x0
numrtids_vc1:
000: 0
001: 1
010: 2
011: 3
100: 4
Others: Reserved
2:2
RW
0x0
pcirdcurr_drduc_sel_vcp:
VCp selection of PCIRdCurrent or DRd.UC
0: PCIRdCurrent
1: DRd.UC
Note: This CSR should always be set to '0' due to Cbo issues in handling VCp 
requests as DRd.UC.
1:1
RW
0x0
diswrcomb:
Causes all writes to send a WB request as soon as M-state is acquired. See 
Section 3.12.2 for details.
0: Enable b2b Write Combining for writes from same port
1: Disable b2b Write Combining for writes from same port
Type:
CFG
PortID:
N/A
Bus:
0
Device:
5Function:0
Offset:
0x140
Bit
Attr
Default
Description
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