Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
411
Datasheet Volume Two: Functional Description, February 2014
Integrated I/O (IIO) Configuration Registers
14.7.11 VTD[0:1]_FLTEVTADDR
Intel
®
VT-d Fault Event Address.
14.7.12 VTD[0:1]_FLTEVTUPRADDR
14.7.13 VTD[0:1]_PMEN
Intel
®
VT-d Protect Memory Enable.
Type:
MEM
PortID:
8’h7e
Bus:
0
Device:
5Function:0
Offset:
0x40, 0x1040
Bit
Attr
Default
Description
31:2
RW
0x0
interrupt_address:
The interrupt address is interpreted as the address of any other interrupt 
from a PCI Express port.
1:0
RV
-
Reserved (Rsvd):
Reserved.
Type:
MEM
PortID:
8’h7e
Bus:
0
Device:
5Function:0
Offset:
0x44
, 0x1044
Bit
Attr
Default
Description
31:0
RW
0x0
address:
Type:
MEM
PortID:
8’h7e
Bus:
0
Device:
5Function:0
Offset:
0x64
, 0x1064
Bit
Attr
Default
Description
31:31
RW
0x0
protmemen:
Enable Protected Memory PROT_LOW_BASE/LIMIT and 
PROT_HIGH_BASE/LIMIT memory regions.
Software can use the protected low/high address ranges to protect both the 
DMA remapping tables and the interrupt remapping tables. There is no 
separate set of registers provided for each.
30:1
RV
-
Reserved.
0:0
RO_V
0x0
protregionsts:
This bit is set by the processor whenever it has completed enabling the 
protected memory region per the rules stated in the Intel
®
VT-d spec 
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