Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
iMC Functional Description
42
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
The memory address decoder supports channel and rank interleaving, several DIMM 
and DRAM device types, and both open and closed page optimized address mappings. 
There is a requirement that at each level of interleaving, the set of targets must each 
contribute an equal amount of memory. For example, 8 GB of system space can be 2-
way socket interleaved, and then 4-way channel interleaved on one socket and 2-way 
channel interleaved on the other. This results in both sockets contributing 4 GB each to 
the interleave, one socket with 4 channels contributing 1 GB each, and the other with 2 
channels contributing 2 GB each.
The decode process is broken into three address translation steps: system to channel, 
channel to rank, and finally rank to DRAM device. The first two steps each involve 
division and subtraction. The division reduces the address space based on the number 
of interleave ways, and the subtraction adjusts for offsets between the different 
address spaces. The rank to DRAM address translation step requires only muxing 
because of the matching address space sizes and lack of interleaving at this level.
5.3.1
Summary of Address Translation
The address map is optimized to speed decode. As many DRAM bits as possible are 
assigned to a single rank address bit, and require no logic to map. The number of times 
a DRAM bit appears in the table indicates the width of the mux used to map address 
bits to the DRAM bit.
Channel address bits are mapped to DRAM bits according to the number of rows, 
columns, banks in the target DIMM, lockstep or independent channels, and scheduling 
policies. Each DIMM may have a different address assignment. 
The following tables describe the translation from System Address to Rank Address to 
the DRAM bits in the memory channel. There are two main tables, for page open and 
closed. Minor variations are shown for independent and lockstep channels. The columns 
on the right show the mapping of system address to rank address for all possible 
combinations of channel and rank interleaves. (The 3 way interleaves represent the 
truncation case. The divide by 3 scheme, the channel address is system address/3). 
Row, Column and Bank bits which are present in all DRAM organizations are 
indicated by a box around the cell in the tables. The other DRAM bits are only present 
in larger DRAMs. 
5.3.2
DRAM Maintenance Operations
The maintenance operations consist of Refresh, DRAM temperature monitoring, Host 
Driver Impedance calibration, and DRAM driver Impedance Calibration. They are made 
as infrequent as the physical process they address to reduce performance impact. 
5.3.3
Refresh
The iMC supports three types of refresh – opportunistic refresh, high-priority refresh 
and panic refresh. Opportunistic refresh is executed when the refresh execution affect 
on normal operation is low. High-priority and panic refreshes are executed when the 
refresh time constrains are close to expire, and refresh must be executed.
The DDR refresh rules are defined in two levels:
1. Refresh of a given page has to occur once every 64 / 32 ms. In order to obtain this, 
the average time between two refreshes is tREFI = 7.8 / 3.9 us (times are for 
normal / high temperature operation).
2. The gap between two successive refreshes may not be more than 9* tREFI.
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