Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
41
Datasheet Volume Two: Functional Description, February 2014
iMC Functional Description
In Intel Xeon processor E7 v2 product family channel 0 can be used to control two 
DDR3 DRAM channels behind the Intel SMI 2 bus in Sub channel lockstep mode, while 
Channel 2 controls two DRAM channels behind a second Intel SMI 2 bus. Each pair of 
channels (Channels 0&1, Channels 2&3) shares a Write Push Logic unit, while each 
channel has a Intel SMI 2 Retry buffer and a Intel SMI 2 Command Encoder.
Read and Write addresses from the HA are steered according to address decode to one 
of the four channels or a pair of channels (in the mirroring or lockstep cases). The 
channels decompose the reads and writes into precharge, activate and column 
commands and schedule their command to the DDR command/address lines. Write 
data is enqueued in the Write Data Buffers where partial writes are merged to form full 
line writes. The Channels drive write data to the DRAMs and the DRAMs return read 
data on the bidirectional data bus. Read returns from the 4 channels are corrected if 
necessary multiplexed back to the HA data buffer.
5.2.2
Logical and Physical Channels
The Memory controller channels exposed to the HA are logical. The HA sends requests 
and maintains credits on a logical channel basis. The memory controller may translate 
the channel select sent by the HA to one or two physical channels. 
5.2.3
Lockstep
Lockstep refers to splitting cache lines across DDR sub channels (off Intel C102/C104 
Scalable Memory Buffer). This is done to support SDDC for DRAM devices with 8-bit 
wide data ports. The same address is used on both channels, such that an address 
error on any channel is detectable by bad ECC. The ECC code used by the memory 
controller can correct 1/18
th
 of the data in a codeword. Since there are 9 x8 DRAMs on 
a DIMM, a codeword must be split across 2 DIMMs to allow the ECC to correct all the 
bits corrupted by a x8 DRAM failure. The MC always accumulates 32B before forwarding 
data so there is no latency benefit for disabling ECC. 
5.2.4
Independent Channel Mode
In x4 DRAM use case, SDDC is supported, and x8 DRAM provides ECC coverage only. 
Each channel is running independently (non-lock-step), that is, each line from memory 
is provided by a channel. To deliver the 64B line of data, each channel is bursting eight 
8B chunks of data. Back to back data transfer in the same direction and within the 
same rank may incur no dead-cycle. The independent channel mode is the 
recommended method to deliver most efficient power and bandwidth. 
For each channel, these connections are made to every rank of every connected DIMM. 
5.3
Memory Address Decode
The memory address decoder (mc_dec) translates a system address into a DRAM 
device address. The main input to the decoder comes from the HA. These inputs are 
the full system address, the target DDR channel, and the TAD range the system 
address falls into. The decoder uses this input and the TAD, RIR, and MTR MSR settings 
to control the decode. The decoder outputs are row, column, and bank DRAM 
addresses, as well as the target rank. While the HA performs some analysis of the 
system address, such as determining the target channel, the MC decoder implements 
all the steps to translate the system address, including removing gaps in the system 
address space that do not map to main memory.
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