Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
99
Datasheet Volume Two: Functional Description, February 2014
Processor Uncore Configuration Registers
13.2.1.10 MH_DTYCYC_MIN_ASRT_CNTR_[0:1]
MEMHOT Duty Cycle Period and Min Assertion Counter.
13.2.1.11 MH_IO_500NS_CNTR
MEMHOT Input Output and 500ns Counter.
9:0
RWS
0x190
CNFG_500_NANOSEC (cnfg_500_nanosec):
500 ns equivalent in DCLK. BIOS calculate number of DCLK to be equivalent to 
500 nanoseconds. This value is loaded into CNTR_500_NANOSEC when it is 
decremented to zero. For presilicon validation, minimum 2 can be set to speed 
up the simulation.
The following are the recommended CNFG_500_NANOSEC values based from 
each DCLK frequency:
DCLK = 400 MHz, CNFG_500_NANOSEC = 0C8h
DCLK = 533 MHz, CNFG_500_NANOSEC = 10Ah
DCLK = 667 MHz, CNFG_500_NANOSEC = 14Dh
DCLK = 800 MHz, CNFG_500_NANOSEC = 190h
DCLK = 933 MHz, CNFG_500_NANOSEC = 1D2h
Type:
CFG
PortID: N/A
Bus:
1
Device: 15
Function:
0
Bus:
1
Device: 29
Function:
0
Offset:
0x10c
Bit
Attr
Default
Description
Type:
CFG
PortID: N/A
Bus:
1
Device: 15
Function:
0
Bus:
1
Device: 29
Function:
0
Offset:
0x110, 0x114
Bit
Attr
Default
Description
31:20
RO_V
0x0
MH_MIN_ASRTN_CNTR (mh_min_asrtn_cntr):
MEM_HOT[1:0]# Minimum Assertion Time Current Count in number of 
CNTR_500_NANOSEC decrement by 1 every CNTR_500_NANOSEC. When the 
counter is zero, the counter is remain at zero and it is only loaded with 
MH_MIN_ASRTN only when MH_DUTY_CYC_PRD_CNTR is reloaded. 
19:0
RW_LV
0x0
MH_DUTY_CYC_PRD_CNTR (mh_duty_cyc_prd_cntr):
MEM_HOT[1:0]# DUTY Cycle Period Current Count in number of 
CNTR_500_NANOSEC decrement by 1 every CNTR_500_NANOSEC. When the 
counter is zero, the next cycle is loaded with MH_DUTY_CYC_PRD. PMSI pause 
(at quiencense) and resume (at wipe).
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