Intel J1850 FH8065301455200 User Manual

Datasheet

1211

The Real Time Clock (RTC) module provides a battery backed-up date and time keeping 
device. Three interrupt features are available: time of day alarm with once a second to 
once a month range, periodic rates of 122 ms to 500 ms, and end of update cycle 
notification. Seconds, minutes, hours, days, day of week, month, and year are counted. 
The hour is represented in twelve or twenty-four hour format, and data can be 
represented in BCD or binary format. The design is meant to be functionally compatible 
with the Motorola MS146818B. The time keeping comes from a 32.768 kHz oscillating 
source, which is divided to achieve an update every second. The lower 14 bytes on the 
lower RAM block have very specific functions. The first ten are for time and date 
information. The next four (0Ah to 0Dh) are registers, which configure and report RTC 
functions. A host-initiated write takes precedence over a hardware update in the event 
of a collision.

An update cycle occurs once a second, if the B.SET bit is not asserted and the divide 
chain is properly configured. During this procedure, the stored time and date are 
incremented, overflow checked, a matching alarm condition is checked, and the time 
and date are rewritten to the RAM locations. The update cycle starts at least 488 ms 

ILB_RTC_X2

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Analog

Crystal Input 2: This signal is connected to the 32.768 kHz crystal. If 

no external crystal is used, the signal should be left floating.

ILB_RTC_RST#

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Digital

RTC Reset: An external RC circuit creates a time delay for the signal 

such that it will go high (de-assert) sometime after the battery 

voltage is valid. The RC time delay should be in the 10-20 ms range
When asserted, this signal resets all register bits in the RTC well 

except for GEN_PMCON1.RPS.

NOTE: Unless registers are being cleared (only to be done in the G3 

power state), the signal input must always be high when all 

other RTC power planes are on.

NOTE: In the case where the RTC battery is dead or missing on the 

platform, the signal should be deasserted before the 

PMC_RSMRST# signal is deasserted.

ILB_RTC_TEST#

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Digital

RTC Battery Test: An external RC circuit creates a time delay for the 

signal such that it will go high (de-assert) sometime after the battery 

voltage is valid. The RC time delay should be in the 10-20 ms range. If 

the battery is missing/weak, this signal appears low (asserted) at boot 

just after the suspend power rail (V3P3A) is up since it will not have 

time to meet Vih when V3P3A is high. The weak/missing battery 

condition is reported in the GEN_PMCON1.RPS (RTC Power Status) 

register. When asserted, BIOS may clear the RTC CMOS RAM.

NOTE: Unless CMOS is being cleared (only to be done in the G3 

power state) or the battery is low, the signal input must 

always be high when all other RTC power planes are on.

NOTE: This signal may also be used for debug purposes, as part of a 

XDP port. 

ILB_RTC_EXTPAD

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Analog

External capacitor connection