Intel J1850 FH8065301455200 User Manual
Product codes
FH8065301455200
PCU – iLB – Real Time Clock (RTC)
1212
Datasheet
after A.UIP is asserted, and the entire cycle does not take more than 1984 ms to
complete. The time and date RAM locations (00h to 09h) are disconnected from the
external bus during this time.
complete. The time and date RAM locations (00h to 09h) are disconnected from the
external bus during this time.
25.3
Interrupts
The real-time clock interrupt is internally routed within the processor both to the I/O
APIC and the 8259. It is mapped to interrupt vector 8. This interrupt does not leave the
processor, nor is it shared with any other interrupt. IRQ8# from the ILB_LPC_SERIRQ
stream is ignored. However, the High Performance Event Timers can also be mapped to
IRQ8#; in this case, the RTC interrupt is blocked.
APIC and the 8259. It is mapped to interrupt vector 8. This interrupt does not leave the
processor, nor is it shared with any other interrupt. IRQ8# from the ILB_LPC_SERIRQ
stream is ignored. However, the High Performance Event Timers can also be mapped to
IRQ8#; in this case, the RTC interrupt is blocked.
25.3.1
Lockable RAM Ranges
The RTC battery-backed RAM supports two 8-byte ranges that can be locked: the RC.UL
and RC.LL register bits. When the locking bits are set, the corresponding range in the
RAM is not readable or writable. A write cycle to those locations will have no effect. A
read cycle to those locations will not return the location’s actual value (resultant value
is undefined).
and RC.LL register bits. When the locking bits are set, the corresponding range in the
RAM is not readable or writable. A write cycle to those locations will have no effect. A
read cycle to those locations will not return the location’s actual value (resultant value
is undefined).
Once a range is locked, the range can be unlocked only by a hard reset, which will
invoke the BIOS and allow it to re-lock the RAM range.
invoke the BIOS and allow it to re-lock the RAM range.
25.3.2
Clearing Battery-Backed RTC CMOS RAM
Clearing CMOS RAM in an processor-based platform can be done by using a jumper on
ILB_RTC_TEST# or a GPI. Implementations should not attempt to clear CMOS by using
a jumper to pull RTC_VCC low.
ILB_RTC_TEST# or a GPI. Implementations should not attempt to clear CMOS by using
a jumper to pull RTC_VCC low.
Note:
The entire Extended Bank and bytes 0Eh-7Fh of the Standard Bank will be cleared.
25.3.2.1
Using ILB_RTC_TEST# to Clear the RTC CMOS RAM
A jumper on ILB_RTC_TEST# can be used to clear CMOS values. When
ILB_RTC_TEST# is low, the GEN_PMCON1.RPS register bit will be set. BIOS can
monitor the state of this bit, and manually clear the RTC CMOS array once the system
is booted. The normal position will cause ILB_RTC_TEST# to be pulled up through a
weak pull-up resistor. This ILB_RTC_TEST# jumper technique allows the jumper to be
moved and then replaced—all while the system is powered off. Then, once booted, the
GEN_PMCON1.RPS bit can be detected in the set state.
ILB_RTC_TEST# is low, the GEN_PMCON1.RPS register bit will be set. BIOS can
monitor the state of this bit, and manually clear the RTC CMOS array once the system
is booted. The normal position will cause ILB_RTC_TEST# to be pulled up through a
weak pull-up resistor. This ILB_RTC_TEST# jumper technique allows the jumper to be
moved and then replaced—all while the system is powered off. Then, once booted, the
GEN_PMCON1.RPS bit can be detected in the set state.
25.3.3
Using a GPI to Clear CMOS
A jumper on a GPI can also be used to clear CMOS values. BIOS should detect the
setting of this GPI on system boot-up, and manually clear the CMOS array.
setting of this GPI on system boot-up, and manually clear the CMOS array.