Intel J1850 FH8065301455200 User Manual
Product codes
FH8065301455200
Datasheet
71
Power Management
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Reduced possible overshoot/undershoot signal quality issues seen by the processor
I/O buffer receivers caused by reflections from potentially un-terminated
transmission lines.
I/O buffer receivers caused by reflections from potentially un-terminated
transmission lines.
When a given rank is not populated, the corresponding chip select and CKE signals are
not driven.
not driven.
At reset, all rows must be assumed to be populated, until it can be proven that they are
not populated. This is due to the fact that when CKE is tri-stated with an SO-DIMM
present, the DIMM is not guaranteed to maintain data integrity.
not populated. This is due to the fact that when CKE is tri-stated with an SO-DIMM
present, the DIMM is not guaranteed to maintain data integrity.
SCKE tri-state should be enabled by BIOS where appropriate, since at reset all rows
must be assumed to be populated.
must be assumed to be populated.
6.4.2
DRAM Power Management and Initialization
The processor implements extensive support for power management on the SDRAM
interface. There are four SDRAM operations associated with the Clock Enable (CKE)
signals, which the SDRAM controller supports. The processor drives four CKE pins to
perform these operations.
interface. There are four SDRAM operations associated with the Clock Enable (CKE)
signals, which the SDRAM controller supports. The processor drives four CKE pins to
perform these operations.
6.4.2.1
Initialization Role of CKE
During power-up, CKE is the only input to the SDRAM that is recognized (other than the
DDR3 reset pin) once power is applied. It must be driven LOW by the DDR controller to
make sure the SDRAM components float DQ and DQS during power-up.
DDR3 reset pin) once power is applied. It must be driven LOW by the DDR controller to
make sure the SDRAM components float DQ and DQS during power-up.
CKE signals remain LOW (while any reset is active) until the BIOS writes to a
configuration register. Using this method, CKE is guaranteed to remain inactive for
much longer than the specified 200 micro-seconds after power and clocks to SDRAM
devices are stable.
configuration register. Using this method, CKE is guaranteed to remain inactive for
much longer than the specified 200 micro-seconds after power and clocks to SDRAM
devices are stable.
6.4.2.2
Conditional Self-Refresh
Intel Rapid Memory Power Management (Intel RMPM) conditionally places memory into
self-refresh in the package C3 and C6 low-power states. RMPM functionality depends
on graphics/display state (relevant only when internal graphics is being used), as well
as memory traffic patterns generated by other connected I/O devices.
self-refresh in the package C3 and C6 low-power states. RMPM functionality depends
on graphics/display state (relevant only when internal graphics is being used), as well
as memory traffic patterns generated by other connected I/O devices.
When entering the Suspend-to-RAM (STR) state, the processor core flushes pending
cycles and then places all SDRAM ranks into self refresh. In STR, the CKE signals
remain LOW so the SDRAM devices perform self-refresh.
cycles and then places all SDRAM ranks into self refresh. In STR, the CKE signals
remain LOW so the SDRAM devices perform self-refresh.
The target behavior is to enter self-refresh for the package C3 and C6 states as long as
there are no memory requests to service.
there are no memory requests to service.