Microchip Technology MCU PIC PIC18F87K22-I/PTRSL TQFP-80 MCP PIC18F87K22-I/PTRSL Data Sheet
Product codes
PIC18F87K22-I/PTRSL
PIC18F87K22 FAMILY
DS39960D-page 366
2009-2011 Microchip Technology Inc.
TABLE 23-2:
REGISTERS ASSOCIATED WITH A/D MODULE
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
GIE/GIEH PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
PIR1
PSPIF
ADIF
RC1IF
TX1IF
SSP1IF
TMR1GIF
TMR2IF
TMR1IF
PIE1
PSPIE
ADIE
RC1IE
TX1IE
SSP1IE
TMR1GIE
TMR2IE
TMR1IE
IPR1
PSPIP
ADIP
RC1IP
TX1IP
SSP1IP
TMR1GIP
TMR2IP
TMR1IP
PIR3
TMR5GIF
—
RC2IF
TX2IF
CTMUIF
CCP2IF
CCP1IF
RTCCIF
PIE3
TMR5GIE
—
RC2IE
TX2IE
CTMUIE
CCP2IE
CCP1IE
RTCCIE
IPR3
TMR5GIP
—
RC2IP
TX2IP
CTMUIP
CCP2IP
CCP1IP
RTCCIP
ADRESH
A/D Result Register High Byte
ADRESL
A/D Result Register Low Byte
ADCON0
—
CHS4
CHS3
CHS2
CHS1
CHS0
GO/DONE
ADON
ADCON1
TRIGSEL1 TRIGSEL0
VCFG1
VCFG0
VNCFG
CHSN2
CHSN1
CHSN0
ADCON2
ADFM
—
ACQT2
ACQT1
ACQT0
ADCS2
ADCS1
ADCS0
ANCON0
ANSEL7
ANSEL6
ANSEL5
ANSEL4
ANSEL3
ANSEL2
ANSEL1
ANSEL0
ANCON1
ANSEL15
ANSEL14
ANSEL13
ANSEL12
ANSEL11
ANSEL10
ANSEL9
ANSEL8
ANCON2
ANSEL23
ANSEL22
ANSEL21
ANSEL20
ANSEL19
ANSEL18
ANSEL17
ANSEL16
CCP2CON
P2M1
P2M0
DC2B1
DC2B0
CCP2M3
CCP2M2
CCP2M1
CCP2M0
PORTA
RA7
(
)
RA6
RA5
RA4
RA3
RA2
RA1
RA0
TRISA
TRISA7
(
)
TRISA6
(
)
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
PORTF
RF7
RF6
RF5
RF4
RF3
RF2
RF1
—
TRISF
TRISF7
TRISF6
TRISF5
TRISF4
TRISF3
TRISF2
TRISF1
—
PORTG
—
—
RG5
RG4
RG3
RG2
RG1
RG0
TRISG
—
—
—
TRISG4
TRISG3
TRISG2
TRISG1
TRISG0
PORTH
(
)
RH7
RH6
RH5
RH4
RH3
RH2
RH1
RH0
TRISH
(
)
TRISH7
TRISH6
TRISH5
TRISH4
TRISH3
TRISH2
TRISH1
TRISH0
PMD0
CCP3MD
CCP2MD
CCP1MD
UART2MD UART1MD
SSP2MD
SSP1MD
ADCMD
Legend:
— = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1:
This register is not implemented on 64-pin devices.
2:
These bits are available only in certain oscillator modes, when the FOSC2 Configuration bit = 0. If that
Configuration bit is cleared, this signal is not implemented.
Configuration bit is cleared, this signal is not implemented.
3:
This bit is available when Master Clear is disabled (MCLRE = 0). When MCLRE is set, the bit is
unimplemented.
unimplemented.