Microchip Technology MCU PIC PIC18F87K22-I/PTRSL TQFP-80 MCP PIC18F87K22-I/PTRSL Data Sheet
Product codes
PIC18F87K22-I/PTRSL
PIC18F87K22 FAMILY
DS39960D-page 364
2009-2011 Microchip Technology Inc.
23.7
A/D Conversions
shows the operation of the A/D Converter
after the GO/DONE bit has been set and the
ACQT<2:0> bits are cleared. A conversion is started
after the following instruction to allow entry into Sleep
mode before the conversion begins.
ACQT<2:0> bits are cleared. A conversion is started
after the following instruction to allow entry into Sleep
mode before the conversion begins.
shows the operation of the A/D Converter
after the GO/DONE bit has been set, the ACQT<2:0>
bits set to ‘010’ and a 4 T
bits set to ‘010’ and a 4 T
AD
acquisition time selected.
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The A/D Result register
pair will NOT be updated with the partially completed
A/D conversion sample. This means the
abort the current conversion. The A/D Result register
pair will NOT be updated with the partially completed
A/D conversion sample. This means the
ADRESH:ADRESL registers will continue to contain
the value of the last completed conversion (or the last
value written to the ADRESH:ADRESL registers).
After the A/D conversion is completed or aborted, a
2 T
the value of the last completed conversion (or the last
value written to the ADRESH:ADRESL registers).
After the A/D conversion is completed or aborted, a
2 T
AD
Wait is required before the next acquisition can
be started. After this Wait, acquisition on the selected
channel is automatically started.
channel is automatically started.
FIGURE 23-6:
A/D CONVERSION T
AD
CYCLES (ACQT<2:0> = 000, T
ACQ
= 0)
FIGURE 23-7:
A/D CONVERSION T
AD
CYCLES (ACQT<2:0> = 010, T
ACQ
= 4 T
AD
)
Note:
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
the same instruction that turns on the A/D.
T
AD
1 T
AD
2 T
AD
3 T
AD
4 T
AD
5 T
AD
6 T
AD
7 T
AD
8
T
AD
11
Set GO/DONE bit
Holding capacitor is disconnected from analog input (typically 100 ns)
T
AD
9 T
AD
10
T
CY
- T
AD
Next Q4: ADRESH:ADRESL is loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
Conversion starts
b2
b11
b8
b7
b6
b5
b4
b3
b10
b9
T
AD
13
T
AD
12
b0
b1
1
2
3
4
5
6
7
8
11
Set GO/DONE bit
(Holding capacitor is disconnected)
9
10
Next Q4: ADRESH:ADRESL is loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is reconnected to analog input.
Conversion starts
1
2
3
4
(Holding capacitor continues
acquiring input)
acquiring input)
T
ACQT
Cycles
T
AD
Cycles
Automatic
Acquisition
Time
Acquisition
Time
b2
b11
b8
b7
b6
b5
b4
b3
b10
b9
13
12
b0
b1