Microchip Technology MCU PIC PIC18F87K22-I/PTRSL TQFP-80 MCP PIC18F87K22-I/PTRSL Data Sheet
Product codes
PIC18F87K22-I/PTRSL
2009-2011 Microchip Technology Inc.
DS39960D-page 365
PIC18F87K22 FAMILY
23.8
Use of the Special Event Triggers
A/D conversion can be started by the Special Event
Trigger of any of these modules:
• ECCP2 – Requires CCP2M<3:0> bits
Trigger of any of these modules:
• ECCP2 – Requires CCP2M<3:0> bits
(CCP2CON<3:0>) set at ‘1011’
• CTMU – Requires the setting of the CTTRIG bit
(CTMUCONH<0>)
• Timer1
• RTCC
To start an A/D conversion:
• The A/D module must be enabled (ADON = 1)
• The appropriate analog input channel is selected
• The minimum acquisition period is set one of
• RTCC
To start an A/D conversion:
• The A/D module must be enabled (ADON = 1)
• The appropriate analog input channel is selected
• The minimum acquisition period is set one of
these ways:
- Timing provided by the user
- Selection made of an appropriate T
- Timing provided by the user
- Selection made of an appropriate T
ACQ
time
With these conditions met, the trigger sets the
GO/DONE bit and the A/D acquisition starts.
If the A/D module is not enabled (ADON = 0), the
module ignores the Special Event Trigger.
GO/DONE bit and the A/D acquisition starts.
If the A/D module is not enabled (ADON = 0), the
module ignores the Special Event Trigger.
23.9
Operation in Power-Managed
Modes
Modes
The selection of the automatic acquisition time and A/D
conversion clock is determined, in part, by the clock
source and frequency while in a power-managed
mode.
If the A/D is expected to operate while the device is in
a power-managed mode, the ACQT<2:0> and
ADCS<2:0> bits in ADCON2 should be updated in
accordance with the power-managed mode clock that
will be used.
After the power-managed mode is entered (either of the
power-managed Run modes), an A/D acquisition or
conversion may be started. Once an acquisition or con-
version is started, the device should continue to be
clocked by the same power-managed mode clock source
until the conversion has been completed. If desired, the
device may be placed into the corresponding
power-managed Idle mode during the conversion.
If the power-managed mode clock frequency is less
than 1 MHz, the A/D RC clock source should be
selected.
Operation in Sleep mode requires that the A/D RC
clock be selected. If bits, ACQT<2:0>, are set to ‘000’
and a conversion is started, the conversion will be
delayed one instruction cycle to allow execution of the
SLEEP
conversion clock is determined, in part, by the clock
source and frequency while in a power-managed
mode.
If the A/D is expected to operate while the device is in
a power-managed mode, the ACQT<2:0> and
ADCS<2:0> bits in ADCON2 should be updated in
accordance with the power-managed mode clock that
will be used.
After the power-managed mode is entered (either of the
power-managed Run modes), an A/D acquisition or
conversion may be started. Once an acquisition or con-
version is started, the device should continue to be
clocked by the same power-managed mode clock source
until the conversion has been completed. If desired, the
device may be placed into the corresponding
power-managed Idle mode during the conversion.
If the power-managed mode clock frequency is less
than 1 MHz, the A/D RC clock source should be
selected.
Operation in Sleep mode requires that the A/D RC
clock be selected. If bits, ACQT<2:0>, are set to ‘000’
and a conversion is started, the conversion will be
delayed one instruction cycle to allow execution of the
SLEEP
instruction and entry into Sleep mode. The
IDLEN and SCS<1:0> bits in the OSCCON register
must have already been cleared prior to starting the
conversion.
must have already been cleared prior to starting the
conversion.
Note:
With an ECCP2 trigger, Timer1 or Timer 3
is cleared. The timers reset to automati-
cally repeat the A/D acquisition period
with minimal software overhead (moving
ADRESH:ADRESL to the desired loca-
tion). If the A/D module is not enabled, the
Special Event Trigger is ignored by the
module, but the timer’s counter resets.
is cleared. The timers reset to automati-
cally repeat the A/D acquisition period
with minimal software overhead (moving
ADRESH:ADRESL to the desired loca-
tion). If the A/D module is not enabled, the
Special Event Trigger is ignored by the
module, but the timer’s counter resets.