Microchip Technology MA330028 Data Sheet
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X
DS80000533H-page 16
2011-2014 Microchip Technology Inc.
25. Module: PWM
Under certain circumstances, an update to the
IOCONx register to turn off the override will be
ignored by the PWM module. The issue has been
observed to occur when the IOCONx update to
turn off the override occurs close to the time when
dead time is being applied.
IOCONx register to turn off the override will be
ignored by the PWM module. The issue has been
observed to occur when the IOCONx update to
turn off the override occurs close to the time when
dead time is being applied.
Work around
1.
Turn off the PWM dead time.
2.
Alternatively, turn off the PWM override with
the following procedure:
the following procedure:
a) Disable the PWM module (PTEN = 0)
b)
Clear the Override Enable bits
(OVRENH = 0 and OVRENL = 0)
(OVRENH = 0 and OVRENL = 0)
c)
Enable the PWM module (PTEN = 1)
Affected Families and Silicon Revisions
26. Module: PWM
In Center-Aligned Complimentary mode with
Independent Time Base, updates to the PHASEx
register take effect after a delay of two PWM
periods.
Independent Time Base, updates to the PHASEx
register take effect after a delay of two PWM
periods.
This occurs only when the Immediate Update
feature is disabled (IUE = 0). If Immediate Update
is enabled (IUE = 1), the PHASEx register updates
will take effect immediately.
feature is disabled (IUE = 0). If Immediate Update
is enabled (IUE = 1), the PHASEx register updates
will take effect immediately.
Work around
None.
Affected Families and Silicon Revisions
27. Module: CTMU
The CTMU cannot be used with the A/D Converter
when the converter is operating in 12-bit mode.
when the converter is operating in 12-bit mode.
Work around
None.
Affected Families and Silicon Revisions
28. Module: Input Capture
When an input capture module is selected as the
Sync source for either an output compare module
or another input capture module, synchronization
may fail.
Sync source for either an output compare module
or another input capture module, synchronization
may fail.
Work around
None.
Affected Families and Silicon Revisions
29. Module: JTAG
The MCLR pin (normally input only) may be set as
an output pin through the JTAG interface. If it is set
at an output high level, subsequent device Resets
are prevented until the device is powered down.
an output pin through the JTAG interface. If it is set
at an output high level, subsequent device Resets
are prevented until the device is powered down.
Work around
None.
Affected Families and Silicon Revisions
dsPIC33/PIC24EP32 devices
A3
dsPIC33/PIC24EP64 devices
A2, A3
dsPIC33/PIC24EP128 devices
A3
dsPIC33/PIC24EP256 devices
A3
dsPIC33/PIC24EP512 devices
See Silicon
Issue
Issue
dsPIC33/PIC24EP32 devices
A3
dsPIC33/PIC24EP64 devices
A2, A3
dsPIC33/PIC24EP128 devices
A3
dsPIC33/PIC24EP256 devices
A3
dsPIC33/PIC24EP512 devices
—
dsPIC33/PIC24EP32 devices
A3
dsPIC33/PIC24EP64 devices
A2, A3, A8
dsPIC33/PIC24EP128 devices
A3, A8
dsPIC33/PIC24EP256 devices
A3
dsPIC33/PIC24EP512 devices
A7
dsPIC33/PIC24EP32 devices
A3
dsPIC33/PIC24EP64 devices
A2, A3, A8
dsPIC33/PIC24EP128 devices
A3, A8
dsPIC33/PIC24EP256 devices
A3
dsPIC33/PIC24EP512 devices
A7
dsPIC33/PIC24EP32 devices
—
dsPIC33/PIC24EP64 devices
—
dsPIC33/PIC24EP128 devices
—
dsPIC33/PIC24EP256 devices
—
dsPIC33/PIC24EP512 devices
—