Microchip Technology MA330028 Data Sheet

Page of 26
 2011-2014 Microchip Technology Inc.
DS80000533H-page  17
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X
30. Module: I/O
On all packages, pins with the following functions 
are not 5V tolerant:
• RC3
• RC4
• RC5
• RA9
Work around
None.
Affected Families and Silicon Revisions
31. Module: JTAG
At a Power-on Reset (POR), when JTAG is 
disabled in the Configuration bits, the I/O pin with 
TMS function produces an active-high logic pulse 
with a pulse width in the order of milliseconds.
Work around
None.
Affected Families and Silicon Revisions
32. Module: QEI
The Velocity Counter (VELxCNT) is a 16-bit wide 
register that increments or decrements based on 
the signal from the quadrature decoder logic. 
Reading this register results in a Counter Reset. 
Typically, the user application should read the 
Velocity Counter at a rate of 1-4 kHz.
As a result of this issue, the Velocity Counter may 
miss a count if the user application reads the 
Velocity Counter register at the same time as a 
(+1 or -1) count increment occurs.
Work around
None.
Affected Families and Silicon Revisions
24EP32/33EP32 devices
A3
24EP64/33EP64 devices
A2, A3
24EP128/33EP128 devices
A3
24EP256/33EP256 devices
A3
dsPIC33/PIC24EP512 devices
dsPIC33/PIC24EP32 devices
A3
dsPIC33/PIC24EP64 devices
A2, A3
dsPIC33/PIC24EP128 devices
A3
dsPIC33/PIC24EP256 devices
A3
dsPIC33/PIC24EP512 devices
dsPIC33/PIC24EP32 devices
A3
dsPIC33/PIC24EP64 devices
A2, A3, A8
dsPIC33/PIC24EP128 devices
A3, A8
dsPIC33/PIC24EP256 devices
A3
dsPIC33/PIC24EP512 devices
A7