Microchip Technology MA330025-1 Data Sheet
2009-2012 Microchip Technology Inc.
DS70616G-page 127
dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
4.4.3
EDS ARBITRATION AND BUS
MASTER PRIORITY
MASTER PRIORITY
EDS accesses from bus masters in the system are
arbitrated.
The arbiter for data memory (including EDS) arbitrates
between the CPU, the DMA, the USB module and the
ICD module. In the event of coincidental access to a
bus by the bus masters, the arbiter determines which
bus master access has the highest priority. The other
bus masters are suspended and processed after the
access of the bus by the bus master with the highest
priority.
By default, the CPU is Bus Master 0 (M0) with the
highest priority and the ICD is Bus Master 4 (M4) with
the lowest priority. The remaining bus masters (USB
and DMA Controllers) are allocated to M2 and M3,
arbitrated.
The arbiter for data memory (including EDS) arbitrates
between the CPU, the DMA, the USB module and the
ICD module. In the event of coincidental access to a
bus by the bus masters, the arbiter determines which
bus master access has the highest priority. The other
bus masters are suspended and processed after the
access of the bus by the bus master with the highest
priority.
By default, the CPU is Bus Master 0 (M0) with the
highest priority and the ICD is Bus Master 4 (M4) with
the lowest priority. The remaining bus masters (USB
and DMA Controllers) are allocated to M2 and M3,
respectively (M1 is reserved and cannot be used). The
user application may raise or lower the priority of the
masters to be above that of the CPU by setting the
appropriate bits in the EDS Bus Master Priority Control
(MSTRPR) register. All bus masters with raised
priorities will maintain the same priority relationship
relative to each other (i.e., M1 being highest and M3
being lowest, with M2 in between). Also, all the bus
masters with priorities below that of the CPU maintain
the same priority relationship relative to each other.
The priority schemes for bus masters with different
MSTRPR values are tabulated in
user application may raise or lower the priority of the
masters to be above that of the CPU by setting the
appropriate bits in the EDS Bus Master Priority Control
(MSTRPR) register. All bus masters with raised
priorities will maintain the same priority relationship
relative to each other (i.e., M1 being highest and M3
being lowest, with M2 in between). Also, all the bus
masters with priorities below that of the CPU maintain
the same priority relationship relative to each other.
The priority schemes for bus masters with different
MSTRPR values are tabulated in
This bus master priority control allows the user
application to manipulate the real-time response of the
system, either statically during initialization, or
dynamically in response to real-time events.
application to manipulate the real-time response of the
system, either statically during initialization, or
dynamically in response to real-time events.
TABLE 4-74:
EDS BUS ARBITER PRIORITY
FIGURE 4-8:
EDS ARBITER ARCHITECTURE
Priority
MSTRPR<15:0> Bit Setting
0x0000
0x0008
0x0020
0x0028
M0 (highest)
CPU
USB
DMA
USB
M1
Reserved
CPU
CPU
DMA
M2
USB
Reserved
Reserved
CPU
M3
DMA
DMA
USB
Reserved
M4 (lowest)
ICD
ICD
ICD
ICD
Note 1: All other values of MSTRPR<15:0> are reserved.
DPSRAM
ICD
USB
EDS Arbiter
M0
M1
M2
M3
M4
Reserved
MSTRPR<15:0>
DMA
CPU
SRAM