Microchip Technology MA330025-1 Data Sheet
dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
DS70616G-page 128
2009-2012 Microchip Technology Inc.
4.4.4
SOFTWARE STACK
The W15 register serves as a dedicated software Stack
Pointer (SP) and is automatically modified by exception
processing, subroutine calls and returns; however,
W15 can be referenced by any instruction in the same
manner as all other W registers. This simplifies
reading, writing and manipulating of the Stack Pointer
(for example, creating stack frames).
Pointer (SP) and is automatically modified by exception
processing, subroutine calls and returns; however,
W15 can be referenced by any instruction in the same
manner as all other W registers. This simplifies
reading, writing and manipulating of the Stack Pointer
(for example, creating stack frames).
W15 is initialized to 0x1000 during all Resets. This
address ensures that the SP points to valid RAM in
all dsPIC33EPXXX(GP/MC/MU)806/810/814 and
PIC24EPXXX(GP/GU)810/814 devices and permits
stack availability for non-maskable trap exceptions.
These can occur before the SP is initialized by the user
software. You can reprogram the SP during
initialization to any location within data space.
The Stack Pointer always points to the first available
free word and fills the software stack working from
lower toward higher addresses.
address ensures that the SP points to valid RAM in
all dsPIC33EPXXX(GP/MC/MU)806/810/814 and
PIC24EPXXX(GP/GU)810/814 devices and permits
stack availability for non-maskable trap exceptions.
These can occur before the SP is initialized by the user
software. You can reprogram the SP during
initialization to any location within data space.
The Stack Pointer always points to the first available
free word and fills the software stack working from
lower toward higher addresses.
illustrates
how it pre-decrements for a stack pop (read) and
post-increments for a stack push (writes).
When the PC is pushed onto the stack, PC<15:0> is
pushed onto the first available stack word, then
PC<22:16> is pushed into the second available stack
location. For a PC push during any CALL instruction,
the MSB of the PC is zero-extended before the push,
as shown in
post-increments for a stack push (writes).
When the PC is pushed onto the stack, PC<15:0> is
pushed onto the first available stack word, then
PC<22:16> is pushed into the second available stack
location. For a PC push during any CALL instruction,
the MSB of the PC is zero-extended before the push,
as shown in
. During exception processing,
the MSB of the PC is concatenated with the lower 8 bits
of the CPU STATUS Register, SR. This allows the
contents of SRL to be preserved automatically during
interrupt processing.
of the CPU STATUS Register, SR. This allows the
contents of SRL to be preserved automatically during
interrupt processing.
FIGURE 4-9:
CALL STACK FRAME
4.5
Instruction Addressing Modes
The addressing modes, shown in
, form the
basis of the addressing modes optimized to support the
specific features of individual instructions. The
addressing modes provided in the MAC class of
instructions differ from those in the other instruction
types.
specific features of individual instructions. The
addressing modes provided in the MAC class of
instructions differ from those in the other instruction
types.
4.5.1
FILE REGISTER INSTRUCTIONS
Most file register instructions use a 13-bit address field
(f) to directly address data present in the first
8192 bytes of data memory (Near Data Space). Most
file register instructions employ a working register, W0,
which is denoted as WREG in these instructions. The
destination is typically either the same file register or
WREG (with the exception of the MUL instruction),
which writes the result to a register or register pair. The
MOV instruction allows additional flexibility and can
access the entire data space.
(f) to directly address data present in the first
8192 bytes of data memory (Near Data Space). Most
file register instructions employ a working register, W0,
which is denoted as WREG in these instructions. The
destination is typically either the same file register or
WREG (with the exception of the MUL instruction),
which writes the result to a register or register pair. The
MOV instruction allows additional flexibility and can
access the entire data space.
4.5.2
MCU INSTRUCTIONS
The three-operand MCU instructions are of the form:
Operand 3 = Operand 1 <function> Operand 2
where Operand 1 is always a working register (that is,
the addressing mode can only be Register Direct),
which is referred to as Wb. Operand 2 can be a W reg-
ister, fetched from data memory, or a 5-bit literal. The
result location can be either a W register or a data
memory location. The following addressing modes are
supported by MCU instructions:
• Register Direct
• Register Indirect
• Register Indirect Post-Modified
• Register Indirect Pre-Modified
• 5-bit or 10-bit Literal
Operand 3 = Operand 1 <function> Operand 2
where Operand 1 is always a working register (that is,
the addressing mode can only be Register Direct),
which is referred to as Wb. Operand 2 can be a W reg-
ister, fetched from data memory, or a 5-bit literal. The
result location can be either a W register or a data
memory location. The following addressing modes are
supported by MCU instructions:
• Register Direct
• Register Indirect
• Register Indirect Post-Modified
• Register Indirect Pre-Modified
• 5-bit or 10-bit Literal
Note:
To protect against misaligned stack
accesses, W15<0> is fixed to ‘0’ by the
hardware.
accesses, W15<0> is fixed to ‘0’ by the
hardware.
Note 1: For main system Stack Pointer (W15)
coherency, W15 is never subject to
(EDS) paging and is therefore,
restricted to the address range of
0x0000 to 0xFFFF. The same applies to
W14 when used as a Stack Frame
Pointer (SFA = 1).
(EDS) paging and is therefore,
restricted to the address range of
0x0000 to 0xFFFF. The same applies to
W14 when used as a Stack Frame
Pointer (SFA = 1).
2: As the stack can be placed in and
across X, Y and DMA RAM spaces,
care must be exercised regarding its
use, particularly with regard to local
automatic variables in a C development
environment.
care must be exercised regarding its
use, particularly with regard to local
automatic variables in a C development
environment.
Note:
Not all instructions support all of the
addressing modes given above. Individ-
ual instructions can support different
subsets of these addressing modes.
addressing modes given above. Individ-
ual instructions can support different
subsets of these addressing modes.
<Free Word>
PC<15:1>
b‘000000000’
0
15
W15 (before CALL)
W15 (after CALL)
S
tac
k Gr
ows
T
owa
rd
Hi
gh
er
A
dd
re
ss
0x0000
PC<22:16>
CALL SUBR