Microchip Technology MA330025-1 Data Sheet
2009-2012 Microchip Technology Inc.
DS70616G-page 601
dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
Revision C (May 2011)
This revision includes minor typographical and
formatting changes throughout the data sheet text.
These global changes were implemented:
• All instances of V
formatting changes throughout the data sheet text.
These global changes were implemented:
• All instances of V
DDCORE
have been removed.
• References to remappable pins have been
updated to clarify output-only pins (RPn) versus
input/output pins (RPIn).
input/output pins (RPIn).
• The minimum V
DD
value was changed from 2.7V to
3.0V to adhere to the current BOR specification.
The major changes are referenced by their respective
section in Table A-2.
section in Table A-2.
TABLE A-2:
MAJOR SECTION UPDATES
Section Name
Update Description
High-Performance, 16-bit Digital
Signal Controllers and
Microcontrollers
Signal Controllers and
Microcontrollers
Removed the shading for D+/RG2 and D-/RG3 pin designations in all pin
diagrams, as these pins are not 5V tolerant.
diagrams, as these pins are not 5V tolerant.
References to remappable pins have been updated to clarify input/output pins
(RPn) and input-only pins (RPIn).
(RPn) and input-only pins (RPIn).
Section 2.0 “Guidelines for
Getting Started with 16-bit Digital
Signal Controllers and
Microcontrollers”
Getting Started with 16-bit Digital
Signal Controllers and
Microcontrollers”
Add information on the V
USB
pin in Section 2.1 “Basic Connection
Requirements”.
Updated the title of Section 2.3 to Section 2.3 “CPU Logic Filter Capacitor
Connection (V
Connection (V
CAP
)” and modified the first paragraph.
Section 3.0 “CPU”
Added Note 2 to the Programmer’s Model Register Descriptions
(see Table 3-1).
(see Table 3-1).
Section 4.0 “Memory
Organization”
Organization”
Added the CANCKS bit (CxCTRL1<11>) to the ECAN1 and ECAN 2 Register
Maps (see Table 4-26 and Table 4-29).
Maps (see Table 4-26 and Table 4-29).
Added the SBOREN bit (RCON<13>) to the System Control Register Map (see
Table 4-43).
Table 4-43).
Added Note 1 to the PORTG Register maps (see Table 4-60 and Table 4-61).
Updated the Page Description for DSRPAG = 0x1FF and DSRPAG = 0x200 in
Table 4-66.
Table 4-66.
Updated the second paragraph of Section 4.2.9 “EDS Arbitration and Bus
Master Priority”.
Master Priority”.
Updated the last note box in Section 4.2.10 “Software Stack”.
Section 5.0 “Flash Program
Memory”
Memory”
Updated the equation formatting in Section 5.3 “Programming Operations”.
Added the Non-Volatile Memory Upper Address (NVMADRU) and Non-Volatile
Memory Address (NVMADR) registers (see Register 5-2 and Register 5-3).
Memory Address (NVMADR) registers (see Register 5-2 and Register 5-3).
Section 6.0 “Resets”
Added Security Reset to the Reset System Block Diagram (see Figure 6-1).
Added the SBOREN bit (RCON<13>) and Notes 3 and 4 to the Reset Control
register (see Register 6-1).
register (see Register 6-1).
Section 11.0 “I/O Ports”
References to remappable pins have been updated to clarify input/output pins
(RPn) and input-only pins (RPIn).
(RPn) and input-only pins (RPIn).
Added the new column, Input/Output, to Input Pin Selection for Selectable Input
Sources (see Table 11-2).
Sources (see Table 11-2).
Section 17.0 “Quadrature
Encoder Interface (QEI) Module
(dsPIC33EPXXXMU806/810/814
Devices Only)”
Encoder Interface (QEI) Module
(dsPIC33EPXXXMU806/810/814
Devices Only)”
Updated the definition for the INTHLD<31:0> bits (see Register 17-19 and
Register 17-20).
Register 17-20).