Microchip Technology MA330025-1 Data Sheet
2009-2012 Microchip Technology Inc.
DS70616G-page 603
dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
Revision D (August 2011)
This revision includes minor typographical and
formatting changes throughout the data sheet text.
The Data Converter Interface (DCI) module is available
on all dsPIC33EPXXX(GP/MC/MU)806/810/814 and
PIC24EPXXX(GP/GU)810/814 devices. References
throughout the document have been updated
accordingly.
formatting changes throughout the data sheet text.
The Data Converter Interface (DCI) module is available
on all dsPIC33EPXXX(GP/MC/MU)806/810/814 and
PIC24EPXXX(GP/GU)810/814 devices. References
throughout the document have been updated
accordingly.
The following pin name changes were implemented
throughout the document:
• C1INA renamed to C1IN1+
• C1INB renamed to C1IN2-
• C1INC renamed to C1IN1-
• C1IND renamed to C1IN3-
• C2INA renamed to C2IN1+
• C2INB renamed to C2IN2-
• C2INC renamed to C2IN1-
• C2IND renamed to C2IN3-
• C3INA renamed to C3IN1+
• C3INB renamed to C3IN2-
• C3INC renamed to C3IN1-
• C3IND renamed to C3IN3-
The other major changes are referenced by their
respective section in Table A-3.
throughout the document:
• C1INA renamed to C1IN1+
• C1INB renamed to C1IN2-
• C1INC renamed to C1IN1-
• C1IND renamed to C1IN3-
• C2INA renamed to C2IN1+
• C2INB renamed to C2IN2-
• C2INC renamed to C2IN1-
• C2IND renamed to C2IN3-
• C3INA renamed to C3IN1+
• C3INB renamed to C3IN2-
• C3INC renamed to C3IN1-
• C3IND renamed to C3IN3-
The other major changes are referenced by their
respective section in Table A-3.
TABLE A-3:
MAJOR SECTION UPDATES
Section Name
Update Description
Section 1.0 “Device Overview”
Added Section 1.1 “Referenced Sources”.
Section 2.0 “Guidelines for Getting
Started with 16-bit Digital Signal
Controllers and Microcontrollers”
Started with 16-bit Digital Signal
Controllers and Microcontrollers”
Updated the Note in Section 2.1 “Basic Connection Requirements”.
Section 3.0 “CPU”
Updated Section 3.1 “Registers”.
Section 4.0 “Memory Organization” Updated FIGURE 4-3: “Data Memory Map for dsPIC33EP512MU810/814
Devices with 52 KB RAM” and FIGURE 4-5: “Data Memory Map for
dsPIC33EP256MU806/810/814 Devices with 28 KB RAM”.
dsPIC33EP256MU806/810/814 Devices with 28 KB RAM”.
Updated the IFS3, IEC3, IPC14, and IPC15 SFRs in the Interrupt Controller
Register Map (see Table 4-6).
Register Map (see Table 4-6).
Updated the SMPI bits for the AD1CON2 and AD2CON2 SFRs in the ADC1
and ADC2 Register Map (see Table 4-23).
and ADC2 Register Map (see Table 4-23).
Updated the All Resets values for the CLKDIV and PLLFBD SFRs and
removed the SBOREN bit in the System Control Register Map
(see Table 4-43).
removed the SBOREN bit in the System Control Register Map
(see Table 4-43).
Section 6.0 “Resets”
Removed the SBOREN bit and Notes 3 and 4 from the Reset Control
Register (see Register 6-1).
Register (see Register 6-1).
Section 8.0 “Direct Memory Access
(DMA)”
(DMA)”
Removed Note 2 from the DMA Channel x IRQ Select Register (see
Register 8-2).
Register 8-2).
Section 9.0 “Oscillator
Configuration”
Configuration”
Updated the PLL Block Diagram (see Figure 9-2).
Updated the value at PORT and the default designations for the
DOZE<2:0>, FRCDIV<2:0>, and PLLPOST<1:0> bits in the Clock Divisor
Register and the PLLDIV<8:0> bits in the PLLFBD register (see Register 9-2
and Register 9-3).
DOZE<2:0>, FRCDIV<2:0>, and PLLPOST<1:0> bits in the Clock Divisor
Register and the PLLDIV<8:0> bits in the PLLFBD register (see Register 9-2
and Register 9-3).
Section 23.0 “10-bit/12-bit Analog-
to-Digital Converter (ADC)”
to-Digital Converter (ADC)”
Added Note 4 and updated the ADC Buffer names in the ADCx Module
Block Diagram (see Figure 23-1).
Block Diagram (see Figure 23-1).
Added Note 3 to the ADCx Control Register 1 (see Register 23-1).
Added the new ADC2 Control Register 2 (see Register 23-3).
Updated the SMPI<4:0> bit value definitions in the ADC1 Control Register 2
(see Register 23-2).
(see Register 23-2).