Microchip Technology MA330028 Data Sheet
2011-2013 Microchip Technology Inc.
DS70000657H-page 153
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
9.0
OSCILLATOR CONFIGURATION
The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/
50X and PIC24EPXXXGP/MC20X oscillator system
provides:
• On-chip Phase-Locked Loop (PLL) to boost
50X and PIC24EPXXXGP/MC20X oscillator system
provides:
• On-chip Phase-Locked Loop (PLL) to boost
internal operating frequency on select internal and
external oscillator sources
external oscillator sources
• On-the-fly clock switching between various clock
sources
• Doze mode for system power savings
• Fail-Safe Clock Monitor (FSCM) that detects clock
• Fail-Safe Clock Monitor (FSCM) that detects clock
failure and permits safe application recovery or
shutdown
shutdown
• Configuration bits for clock source selection
A simplified diagram of the oscillator system is shown
in
A simplified diagram of the oscillator system is shown
in
.
FIGURE 9-1:
OSCILLATOR SYSTEM DIAGRAM
Note 1:
This data sheet summarizes the
features of the dsPIC33EPXXXGP50X,
dsPIC33EPXXXMC20X/50X and
PIC24EPXXXGP/MC20X families of
devices. It is not intended to be a compre-
hensive reference source. To complement
the information in this data sheet, refer to
“Oscillator”
features of the dsPIC33EPXXXGP50X,
dsPIC33EPXXXMC20X/50X and
PIC24EPXXXGP/MC20X families of
devices. It is not intended to be a compre-
hensive reference source. To complement
the information in this data sheet, refer to
“Oscillator”
(DS70580) in the “dsPIC33/
PIC24 Family Reference Manual
”, which is
available from the Microchip web site
(
(
www.microchip.com
).
2:
Some registers and associated bits
described in this section may not be
available on all devices. Refer to
described in this section may not be
available on all devices. Refer to
in
this data sheet for device-specific register
and bit information.
and bit information.
Note
1:
See
2:
The term, F
P
, refers to the clock source for all peripherals, while F
CY
refers to the clock source for the CPU.
Throughout this document, F
CY
and F
P
are used interchangeably, except in the case of Doze mode. F
P
and F
CY
will be different when Doze mode is used with a doze ratio of 1:2 or lower.
XTPLL, HSPLL, ECPLL,
XT, HS, EC
FRCDIV<2:0>
WDT, PWRT,
FRCDIVN
FRCDIV16
NOSC<2:0>
FNOSC<2:0>
Reset
FRC
Oscillator
LPRC
Oscillator
DOZE<2:0>
S3
S1
S2
S1/S3
S7
S6
FRC
LPRC
S0
S5
÷ 16
Clock Switch
0b000
Clock Fail
÷ 2
TUN<5:0>
PLL
(1)
F
CY(2)
F
OSC
F
RCDI
V
DO
Z
E
FSCM
POSCCLK
FRCCLK
OSC2
OSC1
Primary Oscillator
POSCMD<1:0>
F
P(2)
÷ N
ROSEL RODIV<3:0>
REFCLKO
POSCCLK
RPn
F
OSC
Reference Clock Generation
FRCPLL, F
PLLO
COSC<2:0>