Microchip Technology MA330028 Data Sheet
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70000657H-page 154
2011-2013 Microchip Technology Inc.
9.1
CPU Clocking System
The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/
50X and PIC24EPXXXGP/MC20X family of devices
provides six system clock options:
• Fast RC (FRC) Oscillator
• FRC Oscillator with Phase Locked Loop (PLL)
• FRC Oscillator with Postscaler
• Primary (XT, HS or EC) Oscillator
• Primary Oscillator with PLL
• Low-Power RC (LPRC) Oscillator
50X and PIC24EPXXXGP/MC20X family of devices
provides six system clock options:
• Fast RC (FRC) Oscillator
• FRC Oscillator with Phase Locked Loop (PLL)
• FRC Oscillator with Postscaler
• Primary (XT, HS or EC) Oscillator
• Primary Oscillator with PLL
• Low-Power RC (LPRC) Oscillator
Instruction execution speed or device operating
frequency, F
frequency, F
CY
, is given by
EQUATION 9-1:
DEVICE OPERATING
FREQUENCY
FREQUENCY
is a block diagram of the PLL module.
provides the relationship between input
frequency (F
IN
) and output frequency (F
PLLO
). In clock
modes S1 and S3, when the PLL output is selected,
F
F
OSC
= F
PLLO
.
provides the relationship between input
frequency (F
IN
) and VCO frequency (F
VCO
).
FIGURE 9-2:
PLL BLOCK DIAGRAM
EQUATION 9-2:
F
PLLO
CALCULATION
EQUATION 9-3:
F
VCO
CALCULATION
F
CY
= Fosc/2
÷ N1
÷ M
÷ N2
PFD
VCO
PLLPRE<4:0>
PLLDIV<8:0>
PLLPOST<1:0>
0.8 MHz < F
PLLI(1)
< 8.0 MHz
120 MH
Z
< F
VCO(1)
< 340 MH
Z
F
PLLO(1)
120 MHz @ +125ºC
F
IN
F
PLLI
F
VCO
F
PLLO
Note
1:
This frequency range must be met at all times.
F
PLLO(1)
140 MHz @ +85ºC
To F
OSC
clock multiplexer
F
PLLO
F
IN
M
N1
N2
---------------------
F
IN
PLLDIV
2
+
PLLPRE
2
+
2 PLLPOST 1
+
----------------------------------------------------------------------------------------
=
=
Where:
N1 = PLLPRE + 2
N2 = 2 x (PLLPOST + 1)
M = PLLDIV + 2
Fvco
F
IN
M
N1
-------
F
IN
PLLDIV
2
+
PLLPRE
2
+
-------------------------------------
=
=