Microchip Technology MA330028 Data Sheet
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70000657H-page 160
2011-2013 Microchip Technology Inc.
REGISTER 9-3:
PLLFBD: PLL FEEDBACK DIVISOR REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
—
—
—
PLLDIV8
bit 15
bit 8
R/W-0
R/W-0
R/W-1
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
PLLDIV7
PLLDIV6
PLLDIV5
PLLDIV4
PLLDIV3
PLLDIV2
PLLDIV1
PLLDIV0
bit 7
bit 0
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-9
Unimplemented:
Read as ‘0’
bit 8-0
PLLDIV<8:0>:
PLL Feedback Divisor bits (also denoted as ‘M’, PLL multiplier)
111111111
= 513
•
•
•
•
•
000110000
= 50 (default)
•
•
•
•
•
000000010
= 4
000000001
= 3
000000000
= 2