Microchip Technology MA330028 Data Sheet
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70000657H-page 158
2011-2013 Microchip Technology Inc.
REGISTER 9-2:
CLKDIV: CLOCK DIVISOR REGISTER
R/W-0
R/W-0
R/W-1
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
ROI
DOZE2
DOZE1
)
DOZE0
DOZEN
(
FRCDIV2
FRCDIV1
FRCDIV0
bit 15
bit 8
R/W-0
R/W-1
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PLLPOST1
PLLPOST0
—
PLLPRE4
PLLPRE3
PLLPRE2
PLLPRE1
PLLPRE0
bit 7
bit 0
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
ROI:
Recover on Interrupt bit
1
= Interrupts will clear the DOZEN bit
0
= Interrupts have no effect on the DOZEN bit
bit 14-12
DOZE<2:0>:
Processor Clock Reduction Select bits
)
111
= F
CY
divided by 128
110
= F
CY
divided by 64
101
= F
CY
divided by 32
100
= F
CY
divided by 16
011
= F
CY
divided by 8 (default)
010
= F
CY
divided by 4
001
= F
CY
divided by 2
000
= F
CY
divided by 1
bit 11
DOZEN:
Doze Mode Enable bit
(
,
)
1
= DOZE<2:0> field specifies the ratio between the peripheral clocks and the processor clocks
0
= Processor clock and peripheral clock ratio is forced to 1:1
bit 10-8
FRCDIV<2:0>:
Internal Fast RC Oscillator Postscaler bits
111
= FRC divided by 256
110
= FRC divided by 64
101
= FRC divided by 32
100
= FRC divided by 16
011
= FRC divided by 8
010
= FRC divided by 4
001
= FRC divided by 2
000
= FRC divided by 1 (default)
bit 7-6
PLLPOST<1:0>:
PLL VCO Output Divider Select bits (also denoted as ‘N2’, PLL postscaler)
11
= Output divided by 8
10
= Reserved
01
= Output divided by 4 (default)
00
= Output divided by 2
bit 5
Unimplemented:
Read as ‘0’
Note 1:
The DOZE<2:0> bits can only be written to when the DOZEN bit is clear. If DOZEN = 1, any writes to
DOZE<2:0> are ignored.
DOZE<2:0> are ignored.
2:
This bit is cleared when the ROI bit is set and an interrupt occurs.
3:
The DOZEN bit cannot be set if DOZE<2:0> = 000. If DOZE<2:0> = 000, any attempt by user software to
set the DOZEN bit is ignored.
set the DOZEN bit is ignored.