Microchip Technology MA330028 Data Sheet
2011-2013 Microchip Technology Inc.
DS70000657H-page 267
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
18.1
SPI Helpful Tips
1.
In Frame mode, if there is a possibility that the
master may not be initialized before the slave:
a)
master may not be initialized before the slave:
a)
If FRMPOL (SPIxCON2<13>) = 1, use a
pull-down resistor on SSx.
pull-down resistor on SSx.
b)
If FRMPOL = 0, use a pull-up resistor on
SSx.
SSx.
2.
In Non-Framed 3-Wire mode, (i.e., not using
SSx from a master):
a)
SSx from a master):
a)
If CKP (SPIxCON1<6>) = 1, always place a
pull-up resistor on SSx.
pull-up resistor on SSx.
b)
If CKP = 0, always place a pull-down
resistor on SSx.
resistor on SSx.
3.
FRMEN (SPIxCON2<15>) = 1 and SSEN
(SPIxCON1<7>) = 1 are exclusive and invalid.
In Frame mode, SCKx is continuous and the
Frame Sync pulse is active on the SSx pin,
which indicates the start of a data frame.
(SPIxCON1<7>) = 1 are exclusive and invalid.
In Frame mode, SCKx is continuous and the
Frame Sync pulse is active on the SSx pin,
which indicates the start of a data frame.
4.
In Master mode only, set the SMP bit
(SPIxCON1<9>) to a ‘1’ for the fastest SPIx data
rate possible. The SMP bit can only be set at the
same time or after the MSTEN bit
(SPIxCON1<5>) is set.
(SPIxCON1<9>) to a ‘1’ for the fastest SPIx data
rate possible. The SMP bit can only be set at the
same time or after the MSTEN bit
(SPIxCON1<5>) is set.
To avoid invalid slave read data to the master, the
user’s master software must ensure enough time for
slave software to fill its write buffer before the user
application initiates a master write/read cycle. It is
always advisable to preload the SPIxBUF Transmit
register in advance of the next master transaction
cycle. SPIxBUF is transferred to the SPIx Shift register
and is empty once the data transmission begins.
user’s master software must ensure enough time for
slave software to fill its write buffer before the user
application initiates a master write/read cycle. It is
always advisable to preload the SPIxBUF Transmit
register in advance of the next master transaction
cycle. SPIxBUF is transferred to the SPIx Shift register
and is empty once the data transmission begins.
18.2
SPI Resources
Many useful resources are provided on the main prod-
uct page of the Microchip web site for the devices listed
in this data sheet. This product page, which can be
accessed using this
uct page of the Microchip web site for the devices listed
in this data sheet. This product page, which can be
accessed using this
, contains the latest updates
and additional information.
18.2.1
KEY RESOURCES
• “Serial Peripheral Interface (SPI)” (DS70569) in
the “dsPIC33/PIC24 Family Reference Manual”
• Code Samples
• Application Notes
• Software Libraries
• Webinars
• All Related “dsPIC33/PIC24 Family Reference
• Application Notes
• Software Libraries
• Webinars
• All Related “dsPIC33/PIC24 Family Reference
Manual”
Sections
• Development Tools
Note:
This insures that the first frame
transmission after initialization is not
shifted or corrupted.
transmission after initialization is not
shifted or corrupted.
Note:
This will insure that during power-up and
initialization the master/slave will not lose
Sync due to an errant SCKx transition that
would cause the slave to accumulate data
shift errors for both transmit and receive
appearing as corrupted data.
initialization the master/slave will not lose
Sync due to an errant SCKx transition that
would cause the slave to accumulate data
shift errors for both transmit and receive
appearing as corrupted data.
Note:
Not all third-party devices support Frame
mode timing. Refer to the SPIx
specifications in
mode timing. Refer to the SPIx
specifications in
for details.
Note:
In the event you are not able to access the
product page using the link above, enter
this URL in your browser:
product page using the link above, enter
this URL in your browser: