Microchip Technology MA330028 Data Sheet
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70000657H-page 268
2011-2013 Microchip Technology Inc.
18.3
SPIx Control Registers
REGISTER 18-1:
SPIxSTAT: SPIx STATUS AND CONTROL REGISTER
R/W-0
U-0
R/W-0
U-0
U-0
R/W-0
R/W-0
R/W-0
SPIEN
—
SPISIDL
—
—
SPIBEC<2:0>
bit 15
bit 8
R/W-0
R/C-0, HS
R/W-0
R/W-0
R/W-0
R/W-0
R-0, HS, HC R-0, HS, HC
SRMPT
SPIROV
SRXMPT
SISEL2
SISEL1
SISEL0
SPITBF
SPIRBF
bit 7
bit 0
Legend:
C = Clearable bit
HS = Hardware Settable bit
HC = Hardware Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
SPIEN:
SPIx Enable bit
1
= Enables the module and configures SCKx, SDOx, SDIx and SSx as serial port pins
0
= Disables the module
bit 14
Unimplemented:
Read as ‘0’
bit 13
SPISIDL:
SPIx Stop in Idle Mode bit
1
= Discontinues the module operation when device enters Idle mode
0
= Continues the module operation in Idle mode
bit 12-11
Unimplemented:
Read as ‘0’
bit 10-8
SPIBEC<2:0>:
SPIx Buffer Element Count bits (valid in Enhanced Buffer mode)
Master mode:
Number of SPIx transfers that are pending.
Slave mode:
Number of SPIx transfers that are unread.
Number of SPIx transfers that are pending.
Slave mode:
Number of SPIx transfers that are unread.
bit 7
SRMPT:
SPIx Shift Register (SPIxSR) Empty bit (valid in Enhanced Buffer mode)
1
= SPIx Shift register is empty and Ready-To-Send or receive the data
0
= SPIx Shift register is not empty
bit 6
SPIROV:
SPIx Receive Overflow Flag bit
1
= A new byte/word is completely received and discarded; the user application has not read the previous
data in the SPIxBUF register
0
= No overflow has occurred
bit 5
SRXMPT:
SPIx Receive FIFO Empty bit (valid in Enhanced Buffer mode)
1
= RX FIFO is empty
0
= RX FIFO is not empty
bit 4-2
SISEL<2:0>:
SPIx Buffer Interrupt Mode bits (valid in Enhanced Buffer mode)
111
= Interrupt when the SPIx transmit buffer is full (SPITBF bit is set)
110
= Interrupt when last bit is shifted into SPIxSR and as a result, the TX FIFO is empty
101
= Interrupt when the last bit is shifted out of SPIxSR and the transmit is complete
100
= Interrupt when one data is shifted into the SPIxSR and as a result, the TX FIFO has one open
memory location
011
= Interrupt when the SPIx receive buffer is full (SPIRBF bit is set)
010
= Interrupt when the SPIx receive buffer is 3/4 or more full
001
= Interrupt when data is available in the receive buffer (SRMPT bit is set)
000
= Interrupt when the last data in the receive buffer is read and as a result, the buffer is empty
(SRXMPT bit is set)