Microchip Technology DM183037 Data Sheet
2012 Microchip Technology Inc.
DS30575A-page 53
PIC18F97J94 FAMILY
PLL96MHZ submodule runs at 96 MHz and requires an
input clock between 4 MHz and 48 MHz (a multiple of
4 MHz). These are selected through the PLLDIV<3:0>
bits.
input clock between 4 MHz and 48 MHz (a multiple of
4 MHz). These are selected through the PLLDIV<3:0>
bits.
FIGURE 3-7:
BASIC OSCILLATOR BLOCK DIAGRAM
OSCMUX
Divide
by N
FRCDIV
FRC Oscillator (FRC)
Primary Oscillator (POSC)
PLL Module
(PLLM, PLL96MHZ)