Microchip Technology DM183037 Data Sheet
2012 Microchip Technology Inc.
DS30575A-page 55
PIC18F97J94 FAMILY
TABLE 3-3:
SYSTEM CLOCK OPTIONS
DURING USB OPERATION
DURING USB OPERATION
TABLE 3-4:
VALID PRIMARY OSCILLATOR
CONFIGURATIONS FOR USB
OPERATIONS
CONFIGURATIONS FOR USB
OPERATIONS
3.8.2
CONSIDERATIONS FOR USING
THE PLL BLOCK
THE PLL BLOCK
All PLL blocks use the LOCK bit (OSCCON2<5>) as a
read-only status bit to indicate the lock status of the
PLL. It is automatically set after the typical time delay
for the PLL to achieve lock, designated as T
read-only status bit to indicate the lock status of the
PLL. It is automatically set after the typical time delay
for the PLL to achieve lock, designated as T
LOCK
. It is
cleared at a POR and on clock switches when the PLL
is selected as a clock source. It remains clear when any
clock source not using the PLL is selected.
If the PLL does not stabilize properly during start-up,
the LOCK bit may not reflect the actual status of the
PLL lock, nor does it detect when the PLL loses lock
during normal operation. Refer to the ”Electrical Char-
acteristics” section in the specific device data sheet
for further information on the PLL lock interval.
Using any PLL block with the FRC Oscillator provides
a stable system clock for microcontroller operations.
USB operation is only possible with FRC Oscillators
that are implemented with ±1/4% frequency accuracy.
Serial communications using USART are only possible
when FRC Oscillators are implemented with ±2% fre-
quency accuracy. The PIC18F97J94 family is able to
meet the required oscillator accuracy for both USB and
USART providing stable communication by use of its
active clock tuning feature. Refer to
is selected as a clock source. It remains clear when any
clock source not using the PLL is selected.
If the PLL does not stabilize properly during start-up,
the LOCK bit may not reflect the actual status of the
PLL lock, nor does it detect when the PLL loses lock
during normal operation. Refer to the ”Electrical Char-
acteristics” section in the specific device data sheet
for further information on the PLL lock interval.
Using any PLL block with the FRC Oscillator provides
a stable system clock for microcontroller operations.
USB operation is only possible with FRC Oscillators
that are implemented with ±1/4% frequency accuracy.
Serial communications using USART are only possible
when FRC Oscillators are implemented with ±2% fre-
quency accuracy. The PIC18F97J94 family is able to
meet the required oscillator accuracy for both USB and
USART providing stable communication by use of its
active clock tuning feature. Refer to
for more
information.
If an application is being migrated between PIC18F
platforms with different PLL blocks, the differences in
PLL and clock options may require the reconfiguration
of peripherals that use the system clock. This is partic-
ularly true with serial communication peripherals, such
as the USARTs.
If an application is being migrated between PIC18F
platforms with different PLL blocks, the differences in
PLL and clock options may require the reconfiguration
of peripherals that use the system clock. This is partic-
ularly true with serial communication peripherals, such
as the USARTs.
3.9
Secondary Oscillator (SOSC)
In most PIC18F devices, the low-power Secondary
Oscillator (SOSC) is implemented to run with a
32.768 kHz crystal. The oscillator is located on the
SOSCO and SOSCI device pins, and serves as a sec-
ondary crystal clock source for low-power operation. It
is used to drive Timer1, Real-Time Clock and Calendar
(RTCC) and other modules requiring a clock signal
while in low-power operation.
Oscillator (SOSC) is implemented to run with a
32.768 kHz crystal. The oscillator is located on the
SOSCO and SOSCI device pins, and serves as a sec-
ondary crystal clock source for low-power operation. It
is used to drive Timer1, Real-Time Clock and Calendar
(RTCC) and other modules requiring a clock signal
while in low-power operation.
3.9.1
ENABLING THE SECONDARY
OSCILLATOR
OSCILLATOR
The operation of the SOSC is selected by the FOSCx
Configuration bits or by selection of the NOSCx bits
(OSCCON<2:0>). The SOSC can also be enabled by
setting the SOSCEN bit in Timer1, Timer3 or Timer5.
The SOSC has a long start-up time; therefore, to avoid
delays for peripheral start-up, the SOSC can be
manually started using one of the SOSCEN bits.
Configuration bits or by selection of the NOSCx bits
(OSCCON<2:0>). The SOSC can also be enabled by
setting the SOSCEN bit in Timer1, Timer3 or Timer5.
The SOSC has a long start-up time; therefore, to avoid
delays for peripheral start-up, the SOSC can be
manually started using one of the SOSCEN bits.
MCU Clock Division
(CPDIV<1:0>)
System Clock
Frequency
(Instruction Rate in
MIPS)
None (00)
64 MHz (16)
2 (01)
32 MHz (8)
4 (10)
4 MHz (4)
8 (11)
2 MHz (1)
(
)
Note 1: These options are not compatible with
USB operation. They may be used when-
ever the PLL branch is selected and the
USB module is disabled.
ever the PLL branch is selected and the
USB module is disabled.
Input
Oscillator
Frequency
Clock Mode
PLL Division
(PLLDIV<2:0>)
48 MHz
ECPLL
12 (111)
32 MHz
ECPLL
8 (110)
24 MHz
HSPLL, ECPLL
6 (101)
20 MHz
HSPLL, ECPLL
5 (100)
16 MHz
HSPLL, ECPLL
4 (011)
12 MHz
HSPLL, ECPLL
3 (010)
8 MHz
ECPLL, MSPLL,
FRCPLL
(
)
2 (001)
4 MHz
ECPLL, MSPLL,
FRCPLL
(
)
1 (000)
Note 1: FRCPLL with ±0.25% accuracy can be
used for USB operation.
Note:
Because of USB clocking accuracy
requirements (±0.25%), not all PIC18F
devices support the use of the FRCPLL
system clock configuration for USB oper-
ation. Refer to the specific device data
sheet for details on the FRC Oscillator
module.
requirements (±0.25%), not all PIC18F
devices support the use of the FRCPLL
system clock configuration for USB oper-
ation. Refer to the specific device data
sheet for details on the FRC Oscillator
module.