Microchip Technology DM183037 Data Sheet
PIC18F97J94 FAMILY
DS30575A-page 54
2012 Microchip Technology Inc.
3.8.1
OSCILLATOR MODES AND USB
OPERATION
OPERATION
Because of the timing requirements imposed by USB,
an internal clock of 48 MHz is required at all times while
the USB module is enabled and not in a suspended
operating state. A method is provided to internally
generate both the USB and system clocks from a single
oscillator source. PIC18F97J94 family devices use the
same clock structure as most other PIC18 devices, but
include a two-branch PLL system to generate the two
clock signals.
The USB PLL block is shown in
an internal clock of 48 MHz is required at all times while
the USB module is enabled and not in a suspended
operating state. A method is provided to internally
generate both the USB and system clocks from a single
oscillator source. PIC18F97J94 family devices use the
same clock structure as most other PIC18 devices, but
include a two-branch PLL system to generate the two
clock signals.
The USB PLL block is shown in
. In this sys-
tem, the input from the Primary Oscillator is divided
down by a PLL prescaler to generate a 4 MHz output.
down by a PLL prescaler to generate a 4 MHz output.
This is used to drive an on-chip 96 MHz PLL frequency
multiplier to drive the two clock branches. One branch
uses a fixed, divide-by-2 frequency divider to generate
the 48 MHz USB clock. The other branch uses a fixed,
divide-by-1.5 frequency divider and configurable PLL
prescaler/divider to generate a range of system clock
frequencies. The CPDIVx bits select the system clock
speed; available clock options are listed in
multiplier to drive the two clock branches. One branch
uses a fixed, divide-by-2 frequency divider to generate
the 48 MHz USB clock. The other branch uses a fixed,
divide-by-1.5 frequency divider and configurable PLL
prescaler/divider to generate a range of system clock
frequencies. The CPDIVx bits select the system clock
speed; available clock options are listed in
The USB PLL prescaler does not automatically sense
the incoming oscillator frequency. The user must manu-
ally configure the PLL divider to generate the required
4 MHz output, using the PLLDIV<3:0> Configuration
bits. This limits the choices for Primary Oscillator
frequency to a total of 8 possibilities, shown in
the incoming oscillator frequency. The user must manu-
ally configure the PLL divider to generate the required
4 MHz output, using the PLLDIV<3:0> Configuration
bits. This limits the choices for Primary Oscillator
frequency to a total of 8 possibilities, shown in
FIGURE 3-8:
96 MHz PLL BLOCK
96 MHz
PLL
PLL
Pr
esc
aler
PLLDIV<3:0>
Input from
POSC
Input from
FRC
÷12
÷ 8
÷ 6
÷ 5
÷ 4
÷ 8
÷ 6
÷ 5
÷ 4
÷ 3
÷ 2
÷ 1
÷ 1
0111
0110
0101
0100
0011
0010
0001
0000
÷ 2
÷ 1.5
48 MHz Clock
for USB Module
P
osts
claer
÷64
÷63
...
÷17.50
÷17.00
÷63
...
÷17.50
÷17.00
...
÷1.25
127
126
...
65
64
...
1
Clock Output for
Display Interface
(DISPCLK)
÷ 2
0
G1CLKSEL
Graphics Clock
Option 2
P
ostsclaer
CPDIV<1:0>
÷ 8
÷ 4
÷ 2
÷ 1
÷ 4
÷ 2
÷ 1
11
10
01
00
PLL Output for
System Clock
4 MHz or
8 MHz
96 MHz Branch
96 MHz PLL
USB Clock
Graphics Clock
System Clock
4 MHz Branch
48 MHz Branch
FOSC<2:0>