Atmel Evaluation Kit for the SAM4E Series of Flash Microcontrollers ATSAM4E-EK ATSAM4E-EK Data Sheet
Product codes
ATSAM4E-EK
479
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
1.
Set up the transfer type (memory or non-memory peripheral for source and destination) and flow control
device by programming the FC of the DMAC_CTRLBx register.
device by programming the FC of the DMAC_CTRLBx register.
2.
Set up the transfer characteristics, such as:
̶
i. Transfer width for the source in the SRC_WIDTH field.
̶
ii. Transfer width for the destination in the DST_WIDTH field.
̶
v. Incrementing/decrementing or fixed address for source in SRC_INCR field.
̶
vi. Incrementing/decrementing or fixed address for destination DST_INCR field.
3.
Write the starting destination address in the DMAC_DADDRx register for channel x.
Note:
The values in the LLI.DMAC_DADDRx register location of each Linked List Item (LLI) in memory, although fetched
during an LLI fetch, are not used.
during an LLI fetch, are not used.
4.
Write the channel configuration information into the DMAC_CFGx register for channel x.
1.
Designate the handshaking interface type (hardware or software) for the source and destination peripher-
als. This is not required for memory. This step requires programming the SRC_H2SEL/DST_H2SEL bits,
respectively. Writing a ‘1’ activates the hardware handshaking interface to handle source/destination
requests for the specific channel. Writing a ‘0’ activates the software handshaking interface to handle
source/destination requests.
als. This is not required for memory. This step requires programming the SRC_H2SEL/DST_H2SEL bits,
respectively. Writing a ‘1’ activates the hardware handshaking interface to handle source/destination
requests for the specific channel. Writing a ‘0’ activates the software handshaking interface to handle
source/destination requests.
2.
If the hardware handshaking interface is activated for the source or destination peripheral, assign the hand-
shaking interface to the source and destination peripherals. This requires programming the SRC_PER and
DST_PER bits, respectively.
shaking interface to the source and destination peripherals. This requires programming the SRC_PER and
DST_PER bits, respectively.
5.
Make sure that all LLI.DMAC_CTRLBx register locations of the LLI (except the last) are set as shown in Row
2 of Table 26-3 on page 473, while the LLI.DMAC_CTRLBx register of the last Linked List item must be set
as described in Row 1 of Table 26-3 on page 473.
2 of Table 26-3 on page 473, while the LLI.DMAC_CTRLBx register of the last Linked List item must be set
as described in Row 1 of Table 26-3 on page 473.
with two list items.
6.
Make sure that the LLI.DMAC_DSCRx register locations of all LLIs in memory (except the last) are non-zero
and point to the next Linked List Item.
and point to the next Linked List Item.
7.
Make sure that the LLI.DMAC_SADDRx register locations of all LLIs in memory point to the start source
buffer address proceeding that LLI fetch.
buffer address proceeding that LLI fetch.
8.
Make sure that the LLI.DMAC_CTRLAx.DONE field of the LLI.DMAC_CTRLAx register locations of all LLIs
in memory is cleared.
in memory is cleared.
9.
Clear any pending interrupts on the channel from the previous DMAC transfer by reading the interrupt status
register.
register.
10. Program the DMAC_CTRLAx, DMAC_CTRLBx and DMAC_CFGx registers according to Row 2 as shown in
11. Program the DMAC_DSCRx register with DMAC_DSCRx(0), the pointer to the first Linked List item.
12. Finally, enable the channel by writing a ‘1’ to the DMAC_CHER.ENAx bit. The transfer is performed. Make
sure that bit 0 of the DMAC_EN register is enabled.
13. The DMAC fetches the first LLI from the location pointed to by DMAC_DSCRx(0).
Note:
The LLI.DMAC_SADDRx, LLI.DMAC_DADDRx, LLI.DMAC_DSCRx and LLI.DMAC_CTRLA/Bx registers are fetched.
The LLI.DMAC_DADDRx register location of the LLI, although fetched, is not used. The DMAC_DADDRx register in
the DMAC remains unchanged.
The LLI.DMAC_DADDRx register location of the LLI, although fetched, is not used. The DMAC_DADDRx register in
the DMAC remains unchanged.
14. Source and destination requests single and chunk DMAC transactions to transfer the buffer of data
(assuming non-memory peripherals). The DMAC acknowledges at the completion of every transaction
(chunk and single) in the buffer and carries out the buffer transfer.
(chunk and single) in the buffer and carries out the buffer transfer.
15. Once the buffer of data is transferred, the DMAC_CTRLAx register is written out to the system memory at
the same location and on the same layer where it was originally fetched, that is, the location of the
DMAC_CTRLAx register of the linked list item fetched prior to the start of the buffer transfer. Only
DMAC_CTRLAx register is written out because only the DMAC_CTRLAx.BTSIZE and
DMAC_CTRLAX.DONE fields have been updated by DMAC hardware. Additionally, the
DMAC_CTRLAx.DONE bit is asserted when the buffer transfer has completed.
DMAC_CTRLAx register of the linked list item fetched prior to the start of the buffer transfer. Only
DMAC_CTRLAx register is written out because only the DMAC_CTRLAx.BTSIZE and
DMAC_CTRLAX.DONE fields have been updated by DMAC hardware. Additionally, the
DMAC_CTRLAx.DONE bit is asserted when the buffer transfer has completed.