Atmel Evaluation Kit for the SAM4E Series of Flash Microcontrollers ATSAM4E-EK ATSAM4E-EK Data Sheet

SAM4E [DATASHEET]

Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14

480

Note:

Do not poll the DMAC_CTRLAx.DONE bit in the DMAC memory map. Instead, poll the LLI.DMAC_CTRLAx.DONE bit 
in the LLI for that buffer. If the poll LLI.DMAC_CTRLAx.DONE bit is asserted, then this buffer transfer has completed. 
This LLI.DMAC_CTRLAx.DONE bit was cleared at the start of the transfer.

16. The DMAC does not wait for the buffer interrupt to be cleared, but continues and fetches the next LLI from 

the memory location pointed to by the current DMAC_DSCRx register, then automatically reprograms the 
DMAC_SADDRx, DMAC_CTRLAx, DMAC_CTRLBx and DMAC_DSCRx channel registers. The 
DMAC_DADDRx register is left unchanged. The DMAC transfer continues until the DMAC samples the 
DMAC_CTRLAx, DMAC_CTRLBx and DMAC_DSCRx registers at the end of a buffer transfer match that 
described in Row 1 of Table 26-3 on page 473. The DMAC then knows that the previous buffer transferred 
was the last buffer in the DMAC transfer. 

The DMAC transfer might look like that shown in 

. Note that the destination address is

decrementing.

The DMAC transfer flow is shown in 

SADDR(2)

SADDR(1)

SADDR(0)

DADDR(2)

DADDR(1)

DADDR(0)

Buffer 2

Buffer 1

Buffer 0

Buffer 0

Buffer 1

Buffer 2

Address of 

Source Layer

Address of

Destination Layer

Source Buffers

Destination Buffers