Atmel Evaluation Kit for the SAM4E Series of Flash Microcontrollers ATSAM4E-EK ATSAM4E-EK Data Sheet
Product codes
ATSAM4E-EK
481
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
Figure 26-9.
DMAC Transfer Flow for Linked List Source Address and Contiguous Destination Address
26.5.6 Disabling a Channel Prior to Transfer Completion
Under normal operation, the software enables a channel by writing a ‘1’ to the Channel Handler Enable Register,
DMAC_CHER.ENAx, and the hardware disables a channel on transfer completion by clearing the
DMAC_CHSR.ENAx register bit.
DMAC_CHER.ENAx, and the hardware disables a channel on transfer completion by clearing the
DMAC_CHSR.ENAx register bit.
The recommended way for software to disable a channel without losing data is to use the SUSPx bit in conjunction
with the EMPTx bit in the Channel Handler Status Register.
with the EMPTx bit in the Channel Handler Status Register.
Channel enabled by
software
LLI Fetch
Hardware reprograms
SADDRx, CTRLAx,CTRLBx, DSCRx
DMAC buffer transfer
Writeback of control
information of LLI
Is DMAC in
Row 1 ?
Channel disabled by
hardware
Buffer Transfer Completed
Interrupt generated here
DMAC Chained Buffer Transfer
Completed Interrupt generated here
yes
no