Intel Xeon® Processor X3430 (8M Cache, 2.40 GHz) BX80605X3430 User Manual

Product codes
BX80605X3430
Page of 296
Processor Uncore Configuration Registers
252
Intel® Xeon® Processor 3400 Series Datasheet, Volume 2
4.10.27 MC_CHANNEL_0_RX_BGF_SETTINGS
MC_CHANNEL_1_RX_BGF_SETTINGS
These are the parameters used to set the Rx clock crossing BGF.
4.10.28 MC_CHANNEL_0_EW_BGF_SETTINGS
MC_CHANNEL_1_EW_BGF_SETTINGS
These are the parameters used to set the early warning RX clock crossing BGF.
Device:
4, 5
Function: 0
Offset:
C8h
Access as a DWord
Bit
Attr
Default
Description
31:27
RO
0
Reserved
26:24
RW
2
PTRSEP
RX FIFO pointer separation settings. THIS FIELD IS NOT USED BY 
HARDWARE. RX Pointer separation can be modified using the round trip 
setting (larger value causes a larger pointer separation).
23:16
RW
0
OFFSET
RX offset setting.
15:8
RW
1
ALIENRATIO
Qclk to BCLK ratio. RX Alien Ratio setting.
7:0
RW
2
NATIVERATIO
Uclk to BCLK ratio. RX Native Ratio setting.
Device:
4, 5
Function: 0
Offset:
CCh
Access as a DWord
Bit
Attr
Default
Description
31:16
RO
0
Reserved
15:8
RW
1
ALIENRATIO
Dclk to Bclk ratio. Early warning Alien Ratio setting.
7:0
RO
0
Reserved