Intel Xeon® Processor X3430 (8M Cache, 2.40 GHz) BX80605X3430 User Manual

Product codes
BX80605X3430
Page of 296
Processor Uncore Configuration Registers
254
Intel® Xeon® Processor 3400 Series Datasheet, Volume 2
4.10.31 MC_CHANNEL_0_PAGETABLE_PARAMS1
MC_CHANNEL_1_PAGETABLE_PARAMS1
These are the parameters used to control parameters for page closing policies.
4.10.32 MC_CHANNEL_0_PAGETABLE_PARAMS2
MC_CHANNEL_1_PAGETABLE_PARAMS2
These are the parameters used to control parameters for page closing policies.
Device:
4, 5
Function: 0
Offset:
D8h
Access as a DWord
Bit
Attr
Default
Description
31:16
RO
0
Reserved
15:8
RW
0
REQUESTCOUNTER
Upper 8 MSBs of a 12-bit counter. This counter determines the window over 
which the page close policy is evaluated.
7:0
RW
0
ADAPTIVETIMEOUTCOUNTER
Upper 8 MSBs of a 12-bit counter. This counter adapts the interval between 
assertions of the page close flag. For a less aggressive page close, the length 
of the count interval is increased and vice versa for a more aggressive page 
close policy.
Device:
4, 5
Function: 0
Offset:
DCh
Access as a DWord
Bit
Attr
Default
Description
31:28
RO
0
Reserved
27
RW
0
ENABLEADAPTIVEPAGECLOSE
When set, enables Adaptive Page Closing.
26:18
RW
0
MINPAGECLOSELIMIT
Upper 9 MSBs of a 13-bit threshold limit. When the mistake counter falls 
below this threshold, a less aggressive page close interval (larger) is 
selected.
17:9
RW
0
MAXPAGECLOSELIMIT
Upper 9 bits of a 13-bit threshold limit. When the mistake counter exceeds 
this threshold, a more aggressive page close interval (smaller) is selected.
8:0
RW
0
MISTAKECOUNTER
Upper 9 MSBs of a 12-bit counter. This counter adapts the interval 
between assertions of the page close flag. For a less aggressive page 
close, the length of the count interval is increased and vice versa for a 
more aggressive page close policy.