Intel Xeon® Processor X3430 (8M Cache, 2.40 GHz) BX80605X3430 User Manual
Product codes
BX80605X3430
Intel® Xeon® Processor 3400 Series Datasheet, Volume 2
253
Processor Uncore Configuration Registers
4.10.29 MC_CHANNEL_0_EW_BGF_OFFSET_SETTINGS
MC_CHANNEL_1_EW_BGF_OFFSET_SETTINGS
These are the parameters to set the early warning RX clock crossing BGF.
4.10.30 MC_CHANNEL_0_ROUND_TRIP_LATENCY
MC_CHANNEL_1_ROUND_TRIP_LATENCY
These are the parameters to set the early warning RX clock crossing the Bubble
Generator FIFO (BGF) used to go between different clocking domains. These settings
provide the gearing necessary to make that clock crossing.
Generator FIFO (BGF) used to go between different clocking domains. These settings
provide the gearing necessary to make that clock crossing.
Device:
4, 5
Function: 0
Offset:
D0h
Access as a DWord
Bit
Attr
Default
Description
31:16
RO
0
Reserved
15:8
RW
2
EVENOFFSET
Early warning even offset setting.
Early warning even offset setting.
7:0
RW
0
ODDOFFSET
Early warning odd offset setting.
Early warning odd offset setting.
Device:
4, 5
Function: 0
Offset:
D4h
Access as a DWord
Bit
Attr
Default
Description
31:8
RO
0
Reserved
7:0
RW
0
ROUND_TRIP_LATENCY
Round trip latency for reads. Units are in UCLK. This register must be
Round trip latency for reads. Units are in UCLK. This register must be
programmed with the appropriate time for read data to be retuned from the
pads after a READ CAS is sent to the DIMMs.