Intel Xeon® Processor X3430 (8M Cache, 2.40 GHz) BX80605X3430 User Manual
Product codes
BX80605X3430
Intel® Xeon® Processor 3400 Series Datasheet, Volume 2
255
Processor Uncore Configuration Registers
4.10.33 MC_TX_BG_CMD_DATA_RATIO_SETTINGS_CH0
MC_TX_BG_CMD_DATA_RATIO_SETTINGS_CH1
Channel Bubble Generator ratios for CMD and DATA.
4.10.34 MC_TX_BG_CMD_OFFSET_SETTINGS_CH0
MC_TX_BG_CMD_OFFSET_SETTINGS_CH1
Integrated Memory Controller Channel Bubble Generator Offsets for CMD FIFO. The
Data command FIFOs share the settings for channel 0 across all three channels. The
register in Channel 0 must be programmed for all configurations.
Data command FIFOs share the settings for channel 0 across all three channels. The
register in Channel 0 must be programmed for all configurations.
4.10.35 MC_TX_BG_DATA_OFFSET_SETTINGS_CH0
MC_TX_BG_DATA_OFFSET_SETTINGS_CH1
Integrated Memory Controller Channel Bubble Generator Offsets for DATA FIFO.
Device:
4, 5
Function: 0
Offset:
E0h
Access as a DWord
Bit
Attr
Default
Description
31:16
RO
0
Reserved
15:8
RW
0
ALIENRATIO. DCLK to BCLK ratio.
7:0
RW
0
NATIVERATIO. UCLK to BCLK ratio.
Device:
4, 5
Function: 0
Offset:
E4h
Access as a DWord
Bit
Attr
Default
Description
31:10
RO
0
Reserved
9:8
RW
0
PTROFFSET. IFO pointer offset.
7:0
RW
0
BGOFFSET BG offset.
Device:
4, 5
Function: 0
Offset:
E8h
Access as a DWord
Bit
Attr
Default
Description
31:17
RO
0
Reserved
16:14
RW
0
RDPTROFFSET. Read FIFO pointer offset.
13:10
RW
0
WRTPTROFFSET. Write FIFO pointer offset.
9:8
RW
0
PTROFFSET. FIFO pointer offset.
7:0
RW
0
BGOFFSET. BG offset.