Intel Xeon® Processor X3430 (8M Cache, 2.40 GHz) BX80605X3430 User Manual
Product codes
BX80605X3430
System Address Map
274
Intel® Xeon® Processor 3400 Series Datasheet, Volume 2
5.2.2
System DRAM Memory Regions
These address ranges are always mapped to system DRAM memory, regardless of the
system configuration. The top of main memory below 4 GB is defined by the Top of Low
Memory (TOLM). Memory between 4 GB and TOHM is extended system memory. Since
the platform may contain multiple processors, the memory space is divided amongst
the processors. There may be memory holes between each processor’s memory
regions. These system memory regions are either coherent or non-coherent. A set of
range registers in the IIO define a non-coherent memory region
(NcMem.Base/NcMem.Limit) within the system DRAM memory region shown above.
System DRAM memory region outside of this range but within the DRAM region shown
in table above is considered coherent.
system configuration. The top of main memory below 4 GB is defined by the Top of Low
Memory (TOLM). Memory between 4 GB and TOHM is extended system memory. Since
the platform may contain multiple processors, the memory space is divided amongst
the processors. There may be memory holes between each processor’s memory
regions. These system memory regions are either coherent or non-coherent. A set of
range registers in the IIO define a non-coherent memory region
(NcMem.Base/NcMem.Limit) within the system DRAM memory region shown above.
System DRAM memory region outside of this range but within the DRAM region shown
in table above is considered coherent.
For inbound transactions, IIO positively decodes these ranges using a couple of
software programmable range registers. Refer to
software programmable range registers. Refer to
for details of inbound
decoding towards system memory. For outbound transactions, it would be an error for
IIO to receive non-coherent accesses to these addresses from Intel QuickPath
Interconnect, but IIO does not explicitly check for this error condition but would rather
forward such accesses to the subtractive decode port, if one exists downstream, by
virtue of subtractive decoding, else it is master aborted. Refer to
IIO to receive non-coherent accesses to these addresses from Intel QuickPath
Interconnect, but IIO does not explicitly check for this error condition but would rather
forward such accesses to the subtractive decode port, if one exists downstream, by
virtue of subtractive decoding, else it is master aborted. Refer to
further details.
Address Region
From
To
640-KB MS-DOS* Memory
000_0000_0000h
000_0009_FFFFh
1 MB to Top-of-Low-Memory
000_0010_0000h
TOLM
Bottom-of-High-Memory to Top-of-
High-Memory
4 GB
TOHM