Intel Xeon® Processor X3430 (8M Cache, 2.40 GHz) BX80605X3430 User Manual
Product codes
BX80605X3430
System Address Map
272
Intel® Xeon® Processor 3400 Series Datasheet, Volume 2
The processor supports PCI Express* upper pre-fetchable base/limit registers. This
allows the PCI Express unit to claim IO accesses above 36 bits, complying with the PCI
Express Spec. Addressing of greater than 8 GB is allowed on either the DMI Interface or
PCI Express interface. The memory controller supports a maximum of 8 GB of DRAM.
No DRAM memory will be accessible above 8 GB.
allows the PCI Express unit to claim IO accesses above 36 bits, complying with the PCI
Express Spec. Addressing of greater than 8 GB is allowed on either the DMI Interface or
PCI Express interface. The memory controller supports a maximum of 8 GB of DRAM.
No DRAM memory will be accessible above 8 GB.
When running in internal graphics mode, writes to GMADR range linear range are
supported. Write accesses to linear regions are supported from DMI only. Write
accesses to tileX and tileY regions (defined using fence registers) are not supported
from DMI or the PEG port. GMADR read accesses are not supported from either DMI or
PEG.
supported. Write accesses to linear regions are supported from DMI only. Write
accesses to tileX and tileY regions (defined using fence registers) are not supported
from DMI or the PEG port. GMADR read accesses are not supported from either DMI or
PEG.
In the following sections, it is assumed that all of the compatibility memory ranges
reside on the DMI Interface. The exception to this rule is VGA ranges, which may be
mapped to PCI Express, DMI, or to the internal graphics device (IGD). In the absence
of more specific references, cycle descriptions referencing PCI should be interpreted as
the DMI Interface/PCI, while cycle descriptions referencing PCI Express or IGD are
related to the PCI Express bus or the internal graphics device respectively. The
Processor does not remap APIC or any other memory spaces above TOLM. The TOLM
register is set to the appropriate value by BIOS. The reclaim base/reclaim limit
registers remap logical accesses bound for addresses above 4 GB onto physical
addresses that fall within DRAM.
reside on the DMI Interface. The exception to this rule is VGA ranges, which may be
mapped to PCI Express, DMI, or to the internal graphics device (IGD). In the absence
of more specific references, cycle descriptions referencing PCI should be interpreted as
the DMI Interface/PCI, while cycle descriptions referencing PCI Express or IGD are
related to the PCI Express bus or the internal graphics device respectively. The
Processor does not remap APIC or any other memory spaces above TOLM. The TOLM
register is set to the appropriate value by BIOS. The reclaim base/reclaim limit
registers remap logical accesses bound for addresses above 4 GB onto physical
addresses that fall within DRAM.
5.2
Memory Address Space
shows the
IIO
system memory address space. There are three basic regions
of memory address space in the system: address below 1 MB, address between 1 MB
and 4 GB, and address above 4 GB. These regions are described in the following
sections.
and 4 GB, and address above 4 GB. These regions are described in the following
sections.
Throughout this section, there will be references to subtractive decode port. It refers to
the port of IIO that is attached to a legacy PCH (DMI). This port is also the recipient of
all addresses that are not positively decoded towards any PCIE device or towards
memory. Refer to
the port of IIO that is attached to a legacy PCH (DMI). This port is also the recipient of
all addresses that are not positively decoded towards any PCIE device or towards
memory. Refer to
and