Intel Xeon® Processor X3430 (8M Cache, 2.40 GHz) BX80605X3430 User Manual

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Intel® Xeon® Processor 3400 Series Datasheet, Volume 2

This region is used to describe the address range of system memory above the 4-GB 
boundary. IIO forwards all inbound accesses to this region to the system memory port 
(unless any of these access addresses are also marked protected.). A portion of the 
address range within this high system DRAM region could be marked non-coherent 
(using NcMem.Base/NcMem.Limit register) and IIO treats them as non-coherent. All 
other addresses are treated as coherent (unless modified using the NS attributes on 
PCI Express). IIO should not receive outbound accesses to this region, but IIO does not 
explicitly check for this error condition but rather subtractively forwards these accesses 
to the subtractive decode port, if one exists downstream (else it is a programming 
error).

Software must setup this address range such that any recovered DRAM hole from 
below the 4-GB boundary and that might encompass a protected sub-region is not 
included in the range.

The high memory mapped I/O range is located above main memory. This region is used 
to map I/O address requirements above 4-GB range. Each IIO in the system is 
allocated a portion of this system address region and within that portion each PCIe port 
use up a sub-range. Refer to 

 for details of these restrictions. 

Each IIO has a couple of MMIOH address range registers (LMMIOH and GMMIOH) to 
support local and remote peer-to-peer in the MMIOH address range. Refer to 

 for details of inbound and outbound decoding for 

accesses to this region. 

For the processor, LMMIOH range registers define the IIO high memory mapped range. 
GMMIOH.BAS/LIM must be set to the same value as LMMIOH.BASE/LIM.

High System Memory

4 GB

TOHM