Intel Xeon® Processor X3430 (8M Cache, 2.40 GHz) BX80605X3430 User Manual
Product codes
BX80605X3430
Intel® Xeon® Processor 3400 Series Datasheet, Volume 2
281
System Address Map
5.2.6.3
BIOS Notes on Address Allocation above 4 GB
The processor does not support hot added memory. Hence, no special BIOS actions are
required for address allocation above 4 GB to maintain a hole.
Since IIO supports only a single contiguous address range for accesses to system
DRAM above 4 GB, BIOS must make sure that there is enough reserved space gap left
between the top of high memory and the bottom of the MMIOH region, if the system
cares about memory hot add. This gap can be used to address hot added memory in
the system and would fit the constraints imposed by IIO decode mechanism.
DRAM above 4 GB, BIOS must make sure that there is enough reserved space gap left
between the top of high memory and the bottom of the MMIOH region, if the system
cares about memory hot add. This gap can be used to address hot added memory in
the system and would fit the constraints imposed by IIO decode mechanism.
5.2.7
Protected System DRAM Regions
IIO supports three address ranges for protecting various system DRAM regions that
carry protected OS code or other proprietary platform information. The ranges are:
carry protected OS code or other proprietary platform information. The ranges are:
• Intel VT-d protected high range
• Intel VT-d protected low range
• Intel VT-d protected low range
5.3
IO Address Space
There are four classes of I/O addresses that are specifically decoded by the platform:
1. I/O addresses used for VGA controllers.
2. I/O addresses used for ISA aliasing
3. I/O addresses used for the PCI Configuration protocol - CFC/CF8
4. I/O addresses used by downstream PCI/PCIe IO devices, typically legacy devices.
2. I/O addresses used for ISA aliasing
3. I/O addresses used for the PCI Configuration protocol - CFC/CF8
4. I/O addresses used by downstream PCI/PCIe IO devices, typically legacy devices.
The range can be further divided by various downstream ports in the IIO. Each
downstream port in IIO contains a BAR to decode its I/O range. Address that falls
within this range is forwarded to its respective IIO, then subsequently to the
downstream port.
downstream port in IIO contains a BAR to decode its I/O range. Address that falls
within this range is forwarded to its respective IIO, then subsequently to the
downstream port.
5.3.1
VGA I/O Addresses
Legacy VGA device uses up the addresses 3B0h–3BBh, 3C0h–3DFh. Any PCIe, DMI port
in IIO can be a valid target of these address ranges if the VGAEN bit in the peer-to-peer
bridge control register corresponding to that port is set (besides the condition where
these regions are positively decoded within the peer-to-peer I/O address range). In the
outbound direction at the PCI-to-PCI bridge (part of PCIe port) direction, by default,
IIO only decodes the bottom 10 bits of the 16 bit I/O address when decoding this VGA
address range with the VGAEN bit set in the peer-to-peer bridge control register. But
when the VGA16DECEN bit is set in addition to VGAEN being set, IIO performs a full 16
bit decode for that port when decoding the VGA address range outbound. In general,
on outbound accesses to this space, IIO positively decodes the address ranges of all
PCIe ports per the peer-to-peer bridge decoding rules (refer to the PCI-PCI Bridge 1.2
Specification for details). When no target is positively identified, IIO sends it down its
subtractive decode port (if one exists, else, Master Abort).
in IIO can be a valid target of these address ranges if the VGAEN bit in the peer-to-peer
bridge control register corresponding to that port is set (besides the condition where
these regions are positively decoded within the peer-to-peer I/O address range). In the
outbound direction at the PCI-to-PCI bridge (part of PCIe port) direction, by default,
IIO only decodes the bottom 10 bits of the 16 bit I/O address when decoding this VGA
address range with the VGAEN bit set in the peer-to-peer bridge control register. But
when the VGA16DECEN bit is set in addition to VGAEN being set, IIO performs a full 16
bit decode for that port when decoding the VGA address range outbound. In general,
on outbound accesses to this space, IIO positively decodes the address ranges of all
PCIe ports per the peer-to-peer bridge decoding rules (refer to the PCI-PCI Bridge 1.2
Specification for details). When no target is positively identified, IIO sends it down its
subtractive decode port (if one exists, else, Master Abort).