SMSC LAN1198 Manual De Usuario
LAN9118 Family Programmer Reference Guide
Revision 1.0 (12-14-09)
20
SMSC AN 12.12
APPLICATION NOTE
has completed, or else spurious operations could result. Setting of the CSR Address, R/nW and CSR
busy bits can all be done with a single write command to the MAC_CSR_CMD Register.
busy bits can all be done with a single write command to the MAC_CSR_CMD Register.
When using the MII_ACC register to access the PHY registers, the MII W/nR bit sets the data direction
for the MII_Data Register. When MII W/nR is set low, the contents of the PHY Register addressed by
the PHY_Address and MII Register Index fields will be loaded into the MII_Data Register. When the
MII W/nR bit is set high, the contents of the MII_Data Register will be stored into the PHY Register
indicated by the PHY Address and MII Register Index fields. The operation begins when the MII
Busy Bit is written with a 1 by the host. To verify that the operation has completed, the host should
continue polling the MII Busy Bit until it is 0. This verification must be completed before any other
attempts are made to read or write a PHY register, otherwise invalid operation could result. When
initiating a PHY Register access, the entire contents of the MII_ACC Register, including the PHY
Address, MII Register Index, MII W/nR bit and MII Busy bit can all be set in a single operation.
for the MII_Data Register. When MII W/nR is set low, the contents of the PHY Register addressed by
the PHY_Address and MII Register Index fields will be loaded into the MII_Data Register. When the
MII W/nR bit is set high, the contents of the MII_Data Register will be stored into the PHY Register
indicated by the PHY Address and MII Register Index fields. The operation begins when the MII
Busy Bit is written with a 1 by the host. To verify that the operation has completed, the host should
continue polling the MII Busy Bit until it is 0. This verification must be completed before any other
attempts are made to read or write a PHY register, otherwise invalid operation could result. When
initiating a PHY Register access, the entire contents of the MII_ACC Register, including the PHY
Address, MII Register Index, MII W/nR bit and MII Busy bit can all be set in a single operation.
When planning access to the hierarchy of register sets, it is a good idea to serialize access to the MAC
and PHY registers by utilizing a spin lock (under Linux, or its equivalent). One per device should be
sufficient to guarantee that each code sequence in the driver completes without interference from
competing driver threads.
and PHY registers by utilizing a spin lock (under Linux, or its equivalent). One per device should be
sufficient to guarantee that each code sequence in the driver completes without interference from
competing driver threads.
Table 5.5 Media Independent Interface Access/Command Register
MII_ACC
Reserved
(31:16)
PHY Address (15:11)
MII Register Index (10:6)
Reserved
(5:2)
MII
W/nR
MII
Busy