STMicroelectronics M95M02-DRMN6TP Memory IC M95M02-DRMN6TP Hoja De Datos

DocID18203 Rev 8

The Hold condition starts when the Hold (HOLD) signal is driven low when Serial Clock (C) 
is already low (as shown in 

). 

The Hold condition ends when the Hold (HOLD) signal is driven high when Serial Clock (C) 
is already low.

 also shows what happens if the rising and falling edges are not timed to coincide 

with Serial Clock (C) being low.

The Status Register contains a number of status and control bits that can be read or set (as 
appropriate) by specific instructions. See 

 for a 

detailed description of the Status Register bits.

The device features the following data protection mechanisms:
•

Before accepting the execution of the Write and Write Status Register instructions, the 
device checks whether the number of clock pulses comprised in the instructions is a 
multiple of eight.

•

All instructions that modify data must be preceded by a Write Enable (WREN) 
instruction to set the Write Enable Latch (WEL) bit. 

•

The Block Protect (BP1, BP0) bits in the Status Register are used to configure part of 
the memory as read-only.

•

The Write Protect (W) signal is used to protect the Block Protect (BP1, BP0) bits in the 
Status Register.

For any instruction to be accepted, and executed, Chip Select (S) must be driven high after 
the rising edge of Serial Clock (C) for the last bit of the instruction, and before the next rising 
edge of Serial Clock (C).

Two points should be noted in the previous sentence:
•

The “last bit of the instruction” can be the eighth bit of the instruction code, or the eighth 
bit of a data byte, depending on the instruction (except for Read Status Register 
(RDSR) and Read (READ) instructions).

•

The “next rising edge of Serial Clock (C)” might (or might not) be the next bus 
transaction for some other device on the SPI bus.

          

0 0  none

none 

0 

1 

Upper quarter

30000h - 3FFFh 

1 

0 

Upper half 

20000h - 3FFFh 

1 

1 

Whole memory

00000h - 3FFFh