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ATSAM4S-XPLD
718
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
35.7.7 Modem Mode
The USART features modem mode, which enables control of the signals: DTR (Data Terminal Ready), DSR (Data Set
Ready), RTS (Request to Send), CTS (Clear to Send), DCD (Data Carrier Detect) and RI (Ring Indicator). While
operating in modem mode, the USART behaves as a DTE (Data Terminal Equipment) as it drives DTR and RTS and can
detect level change on DSR, DCD, CTS and RI.
Ready), RTS (Request to Send), CTS (Clear to Send), DCD (Data Carrier Detect) and RI (Ring Indicator). While
operating in modem mode, the USART behaves as a DTE (Data Terminal Equipment) as it drives DTR and RTS and can
detect level change on DSR, DCD, CTS and RI.
Setting the USART in modem mode is performed by writing the USART_MODE field in the Mode Register (US_MR) to
the value 0x3. While operating in modem mode the USART behaves as though in asynchronous mode and all the
parameter configurations are available.
the value 0x3. While operating in modem mode the USART behaves as though in asynchronous mode and all the
parameter configurations are available.
The control of the DTR output pin is performed by writing the Control Register (US_CR) with the DTRDIS and DTREN
bits respectively to 1. The disable command forces the corresponding pin to its inactive level, i.e. high. The enable
command forces the corresponding pin to its active level, i.e. low. RTS output pin is automatically controlled in this mode
bits respectively to 1. The disable command forces the corresponding pin to its inactive level, i.e. high. The enable
command forces the corresponding pin to its active level, i.e. low. RTS output pin is automatically controlled in this mode
The level changes are detected on the RI, DSR, DCD and CTS pins. If an input change is detected, the RIIC, DSRIC,
DCDIC and CTSIC bits in the Channel Status Register (US_CSR) are set respectively and can trigger an interrupt. The
status is automatically cleared when US_CSR is read. Furthermore, the CTS automatically disables the transmitter when
it is detected at its inactive state. If a character is being transmitted when the CTS rises, the character transmission is
completed before the transmitter is actually disabled.
DCDIC and CTSIC bits in the Channel Status Register (US_CSR) are set respectively and can trigger an interrupt. The
status is automatically cleared when US_CSR is read. Furthermore, the CTS automatically disables the transmitter when
it is detected at its inactive state. If a character is being transmitted when the CTS rises, the character transmission is
completed before the transmitter is actually disabled.
35.7.8 SPI Mode
The Serial Peripheral Interface (SPI) Mode is a synchronous serial data link that provides communication with external
devices in Master or Slave Mode. It also enables communication between processors if an external processor is
connected to the system.
devices in Master or Slave Mode. It also enables communication between processors if an external processor is
connected to the system.
The Serial Peripheral Interface is essentially a shift register that serially transmits data bits to other SPIs. During a data
transfer, one SPI system acts as the “master” which controls the data flow, while the other devices act as “slaves'' which
have data shifted into and out by the master. Different CPUs can take turns being masters and one master may
simultaneously shift data into multiple slaves. (Multiple Master Protocol is the opposite of Single Master Protocol, where
one CPU is always the master while all of the others are always slaves.) However, only one slave may drive its output to
write data back to the master at any given time.
transfer, one SPI system acts as the “master” which controls the data flow, while the other devices act as “slaves'' which
have data shifted into and out by the master. Different CPUs can take turns being masters and one master may
simultaneously shift data into multiple slaves. (Multiple Master Protocol is the opposite of Single Master Protocol, where
one CPU is always the master while all of the others are always slaves.) However, only one slave may drive its output to
write data back to the master at any given time.
A slave device is selected when its NSS signal is asserted by the master. The USART in SPI Master mode can address
only one SPI Slave because it can generate only one NSS signal.
only one SPI Slave because it can generate only one NSS signal.
The SPI system consists of two data lines and two control lines:
Master Out Slave In (MOSI): This data line supplies the output data from the master shifted into the input of the
slave.
slave.
Master In Slave Out (MISO): This data line supplies the output data from a slave to the input of the master.
Table 35-14. Circuit References
USART Pin
V24
CCITT
Direction
TXD
2
103
From terminal to modem
RTS
4
105
From terminal to modem
DTR
20
108.2
From terminal to modem
RXD
3
104
From modem to terminal
CTS
5
106
From terminal to modem
DSR
6
107
From terminal to modem
DCD
8
109
From terminal to modem
RI
22
125
From terminal to modem