Atmel SAM4S-XPLD Atmel ATSAM4S-XPLD ATSAM4S-XPLD Hoja De Datos
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ATSAM4S-XPLD
719
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Serial Clock (SCK): This control line is driven by the master and regulates the flow of the data bits. The master
may transmit data at a variety of baud rates. The SCK line cycles once for each bit that is transmitted.
may transmit data at a variety of baud rates. The SCK line cycles once for each bit that is transmitted.
Slave Select (NSS): This control line allows the master to select or deselect the slave.
35.7.8.1 Modes of Operation
The USART can operate in SPI Master Mode or in SPI Slave Mode.
Operation in SPI Master Mode is programmed by writing to 0xE the USART_MODE field in the Mode Register. In this
case the SPI lines must be connected as described below:
case the SPI lines must be connected as described below:
The MOSI line is driven by the output pin TXD
The MISO line drives the input pin RXD
The SCK line is driven by the output pin SCK
The NSS line is driven by the output pin RTS
Operation in SPI Slave Mode is programmed by writing to 0xF the USART_MODE field in the Mode Register. In this case
the SPI lines must be connected as described below:
the SPI lines must be connected as described below:
The MOSI line drives the input pin RXD
The MISO line is driven by the output pin TXD
The SCK line drives the input pin SCK
The NSS line drives the input pin CTS
In order to avoid unpredicted behavior, any change of the SPI Mode must be followed by a software reset of the
transmitter and of the receiver (except the initial configuration after a hardware reset).
transmitter and of the receiver (except the initial configuration after a hardware reset).
35.7.8.2 Baud Rate
In SPI Master Mode:
The external clock SCK must not be selected (USCLKS
≠ 0x3), and the bit CLKO must be set to “1” in the Mode
Register (US_MR), in order to generate correctly the serial clock on the SCK pin.
To obtain correct behavior of the receiver and the transmitter, the value programmed in CD must be superior or
equal to 6.
equal to 6.
If the internal clock divided (MCK/DIV) is selected, the value programmed in CD must be even to ensure a 50:50
mark/space ratio on the SCK pin, this value can be odd if the internal clock is selected (MCK).
mark/space ratio on the SCK pin, this value can be odd if the internal clock is selected (MCK).
In SPI Slave Mode:
The external clock (SCK) selection is forced regardless of the value of the USCLKS field in the Mode Register
(US_MR). Likewise, the value written in US_BRGR has no effect, because the clock is provided directly by the
signal on the USART SCK pin.
(US_MR). Likewise, the value written in US_BRGR has no effect, because the clock is provided directly by the
signal on the USART SCK pin.
To obtain correct behavior of the receiver and the transmitter, the external clock (SCK) frequency must be at least
6 times lower than the system clock.
6 times lower than the system clock.